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Issue No.06 - Nov.-Dec. (2012 vol.32)
pp: 28-37
David May , XMOS
ABSTRACT
The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications, and I/O are supported by the instruction set of the XCore processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed.
INDEX TERMS
Instruction sets, Computer architecture, Programming, Registers, Real-time systems, Multithreading, multichip, XMOS architecture, multithreaded processor, XCore processor, XMOS interconnect, energy efficiency, multicore
CITATION
David May, "The XMOS Architecture and XS1 Chips", IEEE Micro, vol.32, no. 6, pp. 28-37, Nov.-Dec. 2012, doi:10.1109/MM.2012.87
REFERENCES
1. D. May, The XMOS XS1 Architecture, XMOS, 2009.
2. C.A.R. Hoare, "Communicating Sequential Processes," Comm. ACM, Aug. 1978, pp. 666-677.
3. Inmos, Occam 2 Reference Manual, Prentice Hall, 1988.
4. D. May, "The Transputer Revisited," Millennial Perspectives in Computer Science, J. Davies, B. Roscoe, and J. Woodcock eds., Palgrave, 2000, pp. 215-228.
5. D. Watt, Programming XC on XMOS Devices, XMOS, 2009.
6. D. May, "The Transputer Implementation of Occam," Proc. 5th Int'l Conf. Fifth-Generation Computer Systems, ICOT, Tokyo, 1984, pp. 533-541.
7. J.S. Kowalik, ed., Parallel MIMD Computation, MIT Press, 1985.
8. D Patterson, "Reduced Instruction Set Computers," Comm. ACM, vol. 28, no. 1, 1985, pp. 8-21.
9. D. May, P.H. Welch, and P. Thompson, Networks, Routers and Transputers, IOS Press, 1993.
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