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The XMOS Architecture and XS1 Chips
Nov.-Dec. 2012 (vol. 32 no. 6)
pp. 28-37
David May, XMOS
The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications, and I/O are supported by the instruction set of the XCore processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed.
Index Terms:
Instruction sets,Computer architecture,Programming,Registers,Real-time systems,Multithreading,multichip,XMOS architecture,multithreaded processor,XCore processor,XMOS interconnect,energy efficiency,multicore
Citation:
David May, "The XMOS Architecture and XS1 Chips," IEEE Micro, vol. 32, no. 6, pp. 28-37, Nov.-Dec. 2012, doi:10.1109/MM.2012.87
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