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The XMOS Architecture and XS1 Chips
Nov.-Dec. 2012 (vol. 32 no. 6)
pp. 28-37
| ASCII Text | x | ||
| David May, "The XMOS Architecture and XS1 Chips," IEEE Micro, vol. 32, no. 6, pp. 28-37, Nov.-Dec., 2012. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2012.87, author = {David May}, title = {The XMOS Architecture and XS1 Chips}, journal ={IEEE Micro}, volume = {32}, number = {6}, issn = {0272-1732}, year = {2012}, pages = {28-37}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2012.87}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - The XMOS Architecture and XS1 Chips IS - 6 SN - 0272-1732 SP28 EP37 EPD - 28-37 A1 - David May, PY - 2012 KW - Instruction sets KW - Computer architecture KW - Programming KW - Registers KW - Real-time systems KW - Multithreading KW - multichip KW - XMOS architecture KW - multithreaded processor KW - XCore processor KW - XMOS interconnect KW - energy efficiency KW - multicore VL - 32 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2012.87
The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications, and I/O are supported by the instruction set of the XCore processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed.
Index Terms:
Instruction sets,Computer architecture,Programming,Registers,Real-time systems,Multithreading,multichip,XMOS architecture,multithreaded processor,XCore processor,XMOS interconnect,energy efficiency,multicore
Citation:
David May, "The XMOS Architecture and XS1 Chips," IEEE Micro, vol. 32, no. 6, pp. 28-37, Nov.-Dec. 2012, doi:10.1109/MM.2012.87
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