September/October 2012 (Vol. 32, No. 5) pp. 4-5
0272-1732/12/$31.00 © 2012 IEEE
Published by the IEEE Computer Society
Published by the IEEE Computer Society
2012 International Symposium on Computer Architecture Influential Paper Award
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This column discusses the winner of the 2012 International Symposium on Computer Architecture Influential Paper Award. It describes, from the point of view of the chair of the committee, what makes the paper influential.
The International Symposium on Computer Architecture (ISCA) Influential Paper Award recognizes the paper from the ISCA proceedings 15 years earlier that has had the most impact on the field (in terms of research, development, products, or ideas) during the intervening years. Candidate papers for the award are selected by the current year's ISCA Program Committee (PC), with the final selection made by a committee consisting of the current ISCA PC Chair (Josep Torrellas), the ACM Special Interest Group on Computer Architecture (SIGARCH) Chair (David Wood), and the IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Chair (David Kaeli). The award includes an honorarium for the authors and a certificate.
The 2012 award was given to the following paper from ISCA 1997: "Complexity-Effective Superscalar Processors" by Subbarao Palacharla, Norman P. Jouppi, and James E. Smith, from the University of Wisconsin-Madison and Digital Equipment Corp. Western Research Laboratory.
The paper uses models and Spice simulations to understand how the delays in key pipeline structures depend on a superscalar processor's issue window size and issue width. The structures studied are those for register renaming, instruction wakeup, selection logic, and operand bypass. In the process, the paper describes the sources that introduce complexity in the pipeline. It shows, for example, that the logic associated with the issue window is likely to limit the clock speed of a superscalar processor. The paper also examines how the use of smaller-feature technologies will impact the analysis.
This paper has indeed been influential, as shown by the approximately 925 citations recorded by Google Scholar—the highest number of all the papers from the 1997 edition of ISCA. The paper has influenced many designers, researchers, and students of out-of-order processors in industry and academia. Several of the PC members in ISCA 2012 have used the paper in courses that they prepared and taught at their universities. It is no exaggeration to say that the paper has spawned a large body of related work over the past 15 years, and that it has influenced many out-of-order processor designs.
While the main reason for the paper's influence is no doubt its technical contributions, I would say that a couple of additional factors also helped make it influential: its timeliness and the simplicity with which it expresses its ideas.
The timing was very good. The paper appeared in 1997, at a time when many in the research and development community were painfully aware that processors were becoming highly complicated. There was no clear idea of how to quantify complexity, or even what contributed to complexity (at least in the public domain). This paper shed light on these issues.
Designers in industry were aware of the paper and had read it. For example, I was on sabbatical at IBM Research in Yorktown Heights, NY, at that time, and there was considerable discussion on simultaneous multithreaded (SMT) processors inside the company (as in other companies as well). The researchers and developers I interacted with had read the paper and were pondering the issues of complexity discussed there, as they considered how to best design an SMT processor.
The research community was also stimulated. The paper was influential in the creation and development of the Workshop on Complexity-Effective Design, a yearly workshop that was held from 2000 to 2006 and was always colocated with a top conference in computer architecture. The first organizers were David Albonesi, Pradip Bose, and Subbarao Palacharla, the first author of the paper. Later, other organizers included Diana Marculescu and Prabhakar Kudva. Such workshop series attracted many attendees, included papers and panels, and were documented in IEEE Micro.
In addition, the paper's dissemination has been helped by the fact that it clearly presents its ideas. It uses a relatively high level of abstraction to describe the pipeline structures and what parameters determine their delay. This description is accessible to people without an advanced understanding of the implementation details of out-of-order superscalar pipelines. Moreover, it provides insightful observations that relate the complexity of pipeline structures with the window size and issue width of the processor. Overall, the authors should be congratulated.
Josep Torrellas is a professor in the Departments of Computer Science and Electrical and Computer Engineering at the University of Illinois. He is the director of the Center for Programmable Extreme Scale Computing and the director of the Illinois-Intel Parallelism Center (I2PC). His research interests include multiprocessor computer architecture, low power, and programmability issues. Torrellas has a PhD in electrical engineering from Stanford University. He is a fellow of IEEE and the ACM.