The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.03 - May/June (2012 vol.32)
pp: 110-121
Ting Cao , Australian National University
Xi Yang , Australian National University
Stephen M. Blackburn , Australian National University
Kathryn S. McKinley , Microsoft Research
ABSTRACT
Systematically exploring power, performance, and energy sheds new light on the clash of two trends that unfolded over the past decade: the rise of parallel processors in response to technology constraints on power, clock speed, and wire delay; and the rise of managed high-level, portable programming languages.
INDEX TERMS
power, performance, measurement, methodology, languages, workload
CITATION
Ting Cao, Xi Yang, Stephen M. Blackburn, Kathryn S. McKinley, "What is Happening to Power, Performance, and Software?", IEEE Micro, vol.32, no. 3, pp. 110-121, May/June 2012, doi:10.1109/MM.2012.20
REFERENCES
1. J.S. Emer and D.W. Clark, "A Characterization of Processor Performance in the VAX-11/780," Proc. 11th Ann. Int'l Symp. Computer Architecture (ISCA 84), ACM, 1984, pp. 301-310.
2. M. Bohr, "A 30-Year Retrospective on Dennard's MOSFET Scaling Paper," IEEE SSCS Newsletter, 2007, pp. 11-13.
3. H. Esmaeilzadeh et al., "Dark Silicon and the End of Multicore Scaling," Proc. 38th Ann. Int'l Symp. Computer Architecture (ISCA 11), ACM, 2011, pp. 365-376.
4. H. Esmaeilzadeh et al., "Looking Back on the Language and Hardware Revolutions: Measured Power, Performance, and Scaling," Proc. 16th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (Asplos 11), ACM, 2011, pp. 319-332.
5. S.M. Blackburn et al., "Wake Up and Smell the Coffee: Evaluation Methodologies for the 21st Century," Comm. ACM, vol. 51, no. 8, 2008, pp. 83-89.
6. E. Le Sueur and G. Heiser, "Dynamic Voltage and Frequency Scaling: The Laws of Diminishing Returns," Proc. Int'l Conf. Power-Aware Computing and Systems (HotPower 10), USENIX Assoc., 2010, pp. 1-8.
7. C. Isci and M. Martonosi, "Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data," Proc. 36th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 36), IEEE CS, 2003, pp. 93-104.
8. W.L. Bircher and L.K. John, "Analysis of Dynamic Power Management on Multi-Core Processors," Proc. 22nd Ann. Int'l Conf. Supercomputing (ICS 08), ACM, 2008, pp. 327-338.
9. H. David et al., "RAPL: Memory Power Estimation and Capping," Proc. ACM/IEEE Int'l Symp. Low-Power Electronics and Design, IEEE CS, 2010, pp. 189-194.
10. O. Azizi et al., "Energy-Performance Tradeoffs in Processor Architecture and Circuit Design: A Marginal Cost Analysis," Proc. 37th Ann Int'l Symp. Computer Architecture (ISCA 10), 2010, pp. 26-36.
11. D.M. Tullsen, S.J. Eggers, and H.M. Levy, "Simultaneous Multithreading: Maximizing On-chip Parallelism," Proc. 22nd Ann. Int'l Symp. Computer Architecture, 1995, pp. 392-403.
12. R. Singhal, "Inside Intel Next Generation Nehalem Microarchitecture," Intel Developer Forum (IDF) presentation, Aug. 2008.
13. S.V. Adve et al., "The Energy Efficiency of CMP vs. SMT for Multimedia Workloads," Proc. 18th Ann. Int'l Conf. Supercomputing (ICS 04), ACM, 2004, pp. 196-206.
30 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool