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Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
May/June 2012 (vol. 32 no. 3)
pp. 70-78
Gabriel H. Loh, Advanced Micro Devices
Mark D. Hill, University of Wisconsin—Madison
This work efficiently enables conventional block sizes for very large die-stacked DRAM caches with two innovations: it makes hits faster with compound-access scheduling and misses faster with a MissMap. The combination of these mechanisms enables the new organization to deliver performance comparable to that of an idealistic DRAM cache that employs an impractically large SRAM-based on-chip tag array.

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Index Terms:
die stacking, caches, memory scheduling, MissMap, compound-access scheduling, DRAM
Citation:
Gabriel H. Loh, Mark D. Hill, "Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap," IEEE Micro, vol. 32, no. 3, pp. 70-78, May-June 2012, doi:10.1109/MM.2012.25
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