This Article 
 Bibliographic References 
 Add to: 
Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
May/June 2012 (vol. 32 no. 3)
pp. 70-78
Gabriel H. Loh, Advanced Micro Devices
Mark D. Hill, University of Wisconsin—Madison
This work efficiently enables conventional block sizes for very large die-stacked DRAM caches with two innovations: it makes hits faster with compound-access scheduling and misses faster with a MissMap. The combination of these mechanisms enables the new organization to deliver performance comparable to that of an idealistic DRAM cache that employs an impractically large SRAM-based on-chip tag array.

1. G.H. Loh and M.D. Hill, "Efficiently Enabling Conventional Block Sizes for Very Large Die-Stacked DRAM Caches," Proc. 44th Ann. IEEE/ACM Int'l Symp. Microarchitecture, ACM, 2011, pp. 454-464.
2. X. Dong et al., "Simple But Effective Heterogeneous Main Memory with On-Chip Memory Controller Support," Proc. ACM/IEEE Int'l Conf. High-Performance Computing, Networking, Storage, and Analysis (SC 10), IEEE CS, 2010, doi:10.1109/SC.2010.50.
3. X. Jiang et al., "CHOP: Adaptive Filter-Based DRAM Caching for CMP Server Platforms," Proc. 16th Int'l Symp. High-Performance Computer Architecture (HPCA 10), IEEE CS, 2010, doi:10.1109/HPCA.2010.5416642.
4. L. Zhao et al., "Exploring DRAM Cache Architectures for CMP Server Platforms," Proc. 25th Int'l Conf. Computer Design, IEEE CS, 2007, pp. 55-62.
5. J. Torrellas, M.S. Lam, and J.L. Hennessy, "False Sharing and Spatial Locality in Multiprocessor Caches," IEEE Trans. Computers, vol. 43, no. 6, 1994, pp. 651-663.
6. J. Jaminger and P. Stenström, "Improvement of Energy-Efficiency in Off-Chip Caches by Selective Prefetching," Microprocessor and Microsystems, vol. 26, no. 3, 2002, pp. 107-121.
7. J.S. Liptay, "Structural Aspects of the System/360 Model 85, Part II: The Cache," IBM Systems J., vol. 7, no. 1, 1968, pp. 15-21.
8. N. Binkert et al., "The Gem5 Simulator," ACM SIGARCH Computer Architecture News, vol. 39, no. 2, 2011, doi:10.1145/2024716.2024718.
9. W.A. Wulf and S.A. McKee, "Hitting the Memory Wall: Implications of the Obvious," Computer Architecture News, vol. 23, no. 1, 1995, pp. 20-24.

Index Terms:
die stacking, caches, memory scheduling, MissMap, compound-access scheduling, DRAM
Gabriel H. Loh, Mark D. Hill, "Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap," IEEE Micro, vol. 32, no. 3, pp. 70-78, May-June 2012, doi:10.1109/MM.2012.25
Usage of this product signifies your acceptance of the Terms of Use.