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Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
May/June 2012 (vol. 32 no. 3)
pp. 70-78
ASCII Text
x 
 
Gabriel H. Loh, Mark D. Hill, "Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap," IEEE Micro, vol. 32, no. 3, pp. 70-78, May/June, 2012.
 
 
BibTex
x
 
@article{ 10.1109/MM.2012.25,
author = {Gabriel H. Loh and Mark D. Hill},
title = {Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap},
journal ={IEEE Micro},
volume = {32},
number = {3},
issn = {0272-1732},
year = {2012},
pages = {70-78},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2012.25},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
IS - 3
SN - 0272-1732
SP70
EP78
EPD - 70-78
A1 - Gabriel H. Loh,
A1 - Mark D. Hill,
PY - 2012
KW - die stacking
KW - caches
KW - memory scheduling
KW - MissMap
KW - compound-access scheduling
KW - DRAM
VL - 32
JA - IEEE Micro
ER -
 
Gabriel H. Loh, Advanced Micro Devices
Mark D. Hill, University of Wisconsin—Madison
This work efficiently enables conventional block sizes for very large die-stacked DRAM caches with two innovations: it makes hits faster with compound-access scheduling and misses faster with a MissMap. The combination of these mechanisms enables the new organization to deliver performance comparable to that of an idealistic DRAM cache that employs an impractically large SRAM-based on-chip tag array.

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Index Terms:
die stacking, caches, memory scheduling, MissMap, compound-access scheduling, DRAM
Citation:
Gabriel H. Loh, Mark D. Hill, "Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap," IEEE Micro, vol. 32, no. 3, pp. 70-78, May-June 2012, doi:10.1109/MM.2012.25
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