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FabScalar: Automating Superscalar Core Design
May/June 2012 (vol. 32 no. 3)
pp. 48-59
Niket K. Choudhary, North Carolina State University
Salil V. Wadhavkar, North Carolina State University
Tanmay A. Shah, North Carolina State University
Hiran Mayukh, North Carolina State University
Jayneel Gandhi, North Carolina State University
Brandon H. Dwiel, North Carolina State University
Sandeep Navada, North Carolina State University
Hashem H. Najaf-abadi, North Carolina State University
Eric Rotenberg, North Carolina State University
Providing multiple superscalar core types on a chip, each tailored to different classes of instruction-level behavior, is an exciting direction for increasing processor performance and energy efficiency. Unfortunately, processor design and verification effort increases with each additional core type, limiting the microarchitectural diversity that can be practically implemented. FabScalar aims to automate superscalar core design, opening up processor design to microarchitectural diversity and its many opportunities.
Index Terms:
superscalar processors, instruction-level parallelism, ILP, heterogeneous (asymmetric) multicore, specialization, design automation
Citation:
Niket K. Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem H. Najaf-abadi, Eric Rotenberg, "FabScalar: Automating Superscalar Core Design," IEEE Micro, vol. 32, no. 3, pp. 48-59, May-June 2012, doi:10.1109/MM.2012.23
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