This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Scalable and Efficient Fine-Grained Cache Partitioning with Vantage
May/June 2012 (vol. 32 no. 3)
pp. 26-37
Daniel Sanchez, Stanford University
Christos Kozyrakis, Stanford University
The Vantage cache-partitioning technique enables configurability and quality-of-service guarantees in large-scale chip multiprocessors with shared caches. Caches can have hundreds of partitions with sizes specified at cache line granularity, while maintaining high associativity and strict isolation among partitions

1. L.R. Hsu et al., "Communist, Utilitarian, and Capitalist Cache Policies on CMPs: Caches as a Shared Resource," Proc. 15th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 06), ACM, 2006, pp. 13-22.
2. M.K. Qureshi and Y.N. Patt, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE CS, 2006, pp. 423-432.
3. G.E. Suh, S. Devadas, and L. Rudolph, "A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning," Proc. 8th Int'l Symp. High-Performance Computer Architecture (HPCA 08), IEEE CS, 2002, pp. 117-128.
4. J.L. Shin et al., "A 40nm 16-Core 128-Thread CMT SPARC SoC Processor," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 10), IEEE Press, pp. 98-99.
5. "TILE-Gx 3000 Series Overview," Tilera, 2011; http://www.tilera.com/sites/default/files/ productbriefsTILE-Gx%203000%20Series%20Brief.pdf .
6. J.H. Kelm et al., "Rigel: An Architecture and Scalable Programming Interface for a 1000-Core Accelerator," Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA 09), ACM, 2009, pp. 140-151.
7. D. Sanchez and C. Kozyrakis, "Vantage: Scalable and Efficient Fine-Grain Cache Partitioning," Proc. 38th Ann. Int'l Symp. Computer Architecture (ISCA 11), ACM, 2011, pp. 57-68.
8. A. Seznec, "A Case for Two-Way Skewed-Associative Caches," Proc. 20th Ann. Int'l Symp. Computer Architecture (ISCA 93), ACM, 1993, pp. 169-178.
9. D. Sanchez and C. Kozyrakis, "The ZCache: Decoupling Ways and Associativity," Proc. 43rd Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE CS, 2010, pp. 187-198.
10. D. Chiou et al., "Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches," Proc. 37th Design Automation Conf. (DAC 00), ACM, 2000, pp. 416-419.
11. Y. Xie and G.H. Loh, "PIPP: Promotion/Insertion Pseudo-partitioning of Multi-core Shared Caches," Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA 09), ACM, 2009, pp. 174-183.
1. D. Chiou et al., "Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches," Proc. 37th Design Automation Conf. (DAC 00), ACM Press, 2000, pp. 416-419.
2. P. Ranganathan, S. Adve, and N.P. Jouppi, "Reconfigurable Caches and Their Application to Media Processing," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA 00), ACM, 2000, pp. 214-224.
3. K. Varadarajan et al., "Molecular Caches: A Caching Structure for Dynamic Creation of Application-Specific Heterogeneous Cache Regions," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE CS, 2006, pp. 433-442.
4. J. Lin et al., "Gaining Insights into Multicore Cache Partitioning: Bridging the Gap between Simulation and Real Systems," Proc. 14th Int'l Symp. High-Performance Computer Architecture (HPCA 08), IEEE CS, 2008, pp. 367-378.
5. C.-J. Wu and M. Martonosi, "A Comparison of Capacity Management Schemes for Shared CMP Caches," Proc. 7th Ann. Workshop Duplicating, Deconstructing, and Debunking (WDDD 08), IEEE CS, 2008; http://www.princeton.edu/~carolewuWDDD08-CJW.pdf .
6. Y. Xie and G.H. Loh, "PIPP: Promotion/Insertion Pseudo-partitioning of Multi-core Shared Caches," Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA 09), ACM, 2009, pp. 174-183.

Index Terms:
cache memories, design styles, memory structures, hardware, parallel architectures, processor architectures, computer systems organization, memory hierarchy, microarchitecture implementation considerations, processor architectures, computer systems organization, Vantage, cache partitioning, CMP, QoS
Citation:
Daniel Sanchez, Christos Kozyrakis, "Scalable and Efficient Fine-Grained Cache Partitioning with Vantage," IEEE Micro, vol. 32, no. 3, pp. 26-37, May-June 2012, doi:10.1109/MM.2012.19
Usage of this product signifies your acceptance of the Terms of Use.