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The IBM Blue Gene/Q Compute Chip
March/April 2012 (vol. 32 no. 2)
pp. 48-60
Ruud A. Haring, IBM T.J. Watson Research Center
Martin Ohmacht, IBM T.J. Watson Research Center
Thomas W. Fox, IBM T.J. Watson Research Center
Michael K. Gschwind, IBM T.J. Watson Research Center
David L. Satterfield, IBM T.J. Watson Research Center
Krishnan Sugavanam, IBM T.J. Watson Research Center
Paul W. Coteus, IBM T.J. Watson Research Center
Philip Heidelberger, IBM T.J. Watson Research Center
Matthias A. Blumrich, IBM T.J. Watson Research Center
Robert W. Wisniewski, IBM T.J. Watson Research Center
Alan Gara, IBM T.J. Watson Research Center
George Liang-Tai Chiu, IBM T.J. Watson Research Center
Peter A. Boyle, University of Edinburgh
Norman H. Chist, Columbia University
Changhoan Kim, AIKEN BNL Research Center

Blue Gene/Q aims to build a massively parallel high-performance computing system out of power-efficient processor chips, resulting in power-efficient, cost-efficient, and floor-space-efficient systems. Focusing on reliability during design helps with scaling to large systems and lowers the total cost of ownership. This article examines the architecture and design of the Compute chip, which combines processors, memory, and communication functions on a single chip.

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Index Terms:
Super (very large) computers, large and medium ("mainframe") computers, microprocessors and microcomputers, multithreaded processors, parallel processors, multiple data stream architectures (multiprocessors), SIMD processors, multicore/single-chip multiprocessors, speculative multithreading, support for multithreaded execution
Citation:
Ruud A. Haring, Martin Ohmacht, Thomas W. Fox, Michael K. Gschwind, David L. Satterfield, Krishnan Sugavanam, Paul W. Coteus, Philip Heidelberger, Matthias A. Blumrich, Robert W. Wisniewski, Alan Gara, George Liang-Tai Chiu, Peter A. Boyle, Norman H. Chist, Changhoan Kim, "The IBM Blue Gene/Q Compute Chip," IEEE Micro, vol. 32, no. 2, pp. 48-60, March-April 2012, doi:10.1109/MM.2011.108
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