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| Ruud A. Haring, Martin Ohmacht, Thomas W. Fox, Michael K. Gschwind, David L. Satterfield, Krishnan Sugavanam, Paul W. Coteus, Philip Heidelberger, Matthias A. Blumrich, Robert W. Wisniewski, Alan Gara, George Liang-Tai Chiu, Peter A. Boyle, Norman H. Chist, Changhoan Kim, "The IBM Blue Gene/Q Compute Chip," IEEE Micro, vol. 32, no. 2, pp. 48-60, March/April, 2012. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2011.108, author = {Ruud A. Haring and Martin Ohmacht and Thomas W. Fox and Michael K. Gschwind and David L. Satterfield and Krishnan Sugavanam and Paul W. Coteus and Philip Heidelberger and Matthias A. Blumrich and Robert W. Wisniewski and Alan Gara and George Liang-Tai Chiu and Peter A. Boyle and Norman H. Chist and Changhoan Kim}, title = {The IBM Blue Gene/Q Compute Chip}, journal ={IEEE Micro}, volume = {32}, number = {2}, issn = {0272-1732}, year = {2012}, pages = {48-60}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2011.108}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - The IBM Blue Gene/Q Compute Chip IS - 2 SN - 0272-1732 SP48 EP60 EPD - 48-60 A1 - Ruud A. Haring, A1 - Martin Ohmacht, A1 - Thomas W. Fox, A1 - Michael K. Gschwind, A1 - David L. Satterfield, A1 - Krishnan Sugavanam, A1 - Paul W. Coteus, A1 - Philip Heidelberger, A1 - Matthias A. Blumrich, A1 - Robert W. Wisniewski, A1 - Alan Gara, A1 - George Liang-Tai Chiu, A1 - Peter A. Boyle, A1 - Norman H. Chist, A1 - Changhoan Kim, PY - 2012 KW - Super (very large) computers KW - large and medium ("mainframe") computers KW - microprocessors and microcomputers KW - multithreaded processors KW - parallel processors KW - multiple data stream architectures (multiprocessors) KW - SIMD processors KW - multicore/single-chip multiprocessors KW - speculative multithreading KW - support for multithreaded execution VL - 32 JA - IEEE Micro ER - | |||
Blue Gene/Q aims to build a massively parallel high-performance computing system out of power-efficient processor chips, resulting in power-efficient, cost-efficient, and floor-space-efficient systems. Focusing on reliability during design helps with scaling to large systems and lowers the total cost of ownership. This article examines the architecture and design of the Compute chip, which combines processors, memory, and communication functions on a single chip.
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