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Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge
March/April 2012 (vol. 32 no. 2)
pp. 20-27

Modern microprocessors are evolving into system-on-a-chip designs with high integration levels, catering to ever-shrinking form factors. Portability without compromising performance is a driving market need. An architectural approach that's adaptive to and cognizant of workload behavior and platform physical constraints is indispensable to meeting these performance and efficiency goals. This article describes power-management innovations introduced on Intel's Sandy Bridge microprocessor.

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8. M. Berktold and T. Tian, "CPU Monitoring with DTS/PECI," white paper, Intel, Sept. 2010.
9. Intersil, Power Management Products—Processor Power, 2012; http://www.intersil.comprocessor_power.

Index Terms:
power management, energy management, Turbo Boost, Sandy Bridge
Citation:
Efraim Rotem, Alon Naveh, Avinash Ananthakrishnan, Doron Rajwan, Eliezer Weissmann, "Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge," IEEE Micro, vol. 32, no. 2, pp. 20-27, March-April 2012, doi:10.1109/MM.2012.12
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