This Article 
 Bibliographic References 
 Add to: 
Sparc T4: A Dynamically Threaded Server-on-a-Chip
March/April 2012 (vol. 32 no. 2)
pp. 8-19
Manish Shah, Oracle
Robert Golla, Oracle
Paul Jordan, Oracle
Jama Barreh, Oracle
Jeff Brooks, Oracle
Mark Luttrell, Oracle
Zeid Samoail, Oracle
Matt Smittle, Oracle
Tom Ziaja, Oracle

The Sparc T4 is the next generation of Oracle's multicore, multithreaded 64-bit Sparc server processor. It delivers significant performance improvements over its predecessor, the Sparc T3 processor. The authors describe Sparc T4's key features and detail the microarchitecture of the dynamically threaded S3 processor core, which is implemented on Sparc T4.

1. P. Kongetira et al., "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, 2005, pp. 21-29.
2. G. Grohoski, "Niagara-2: A Highly Threaded Server-on-a-Chip," 18th Hot Chips Symp., 2006, .
3. M. Shah et al., "UltraSparc T2: A Highly-Threaded, Power-Efficient, Sparc SoC," Proc. IEEE Asian Solid-State Circuits Conf., IEEE CS Press, 2007, pp. 22-25.
4. S. Patel et al., "Sun's Next-Generation Multithreaded Processor: Rainbow Falls," 21st Hot Chips Symp., 2009, .
5. D. Jimenez and C. Lin, "Neural Methods for Dynamic Branch Prediction," ACM Trans. Computer Systems, vol. 20, no. 4, 2002, pp. 369-397.

Index Terms:
Microprocessors, computer architecture, multithreaded processors, processor architectures, pipeline processors, computer systems organization, support for security, microarchitecture implementation considerations, multicore/single-chip multiprocessors, parallel architectures, support for multithreaded execution
Manish Shah, Robert Golla, Gregory Grohoski, Paul Jordan, Jama Barreh, Jeff Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Tom Ziaja, "Sparc T4: A Dynamically Threaded Server-on-a-Chip," IEEE Micro, vol. 32, no. 2, pp. 8-19, March-April 2012, doi:10.1109/MM.2012.1
Usage of this product signifies your acceptance of the Terms of Use.