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Issue No.06 - Nov.-Dec. (2011 vol.31)
pp: 39-50
Sugako Otani , Renesas Electronics
Hiroyuki Kondo , Renesas Electronics
Itaru Nonomura , Renesas Electronics
Toshihiro Hanawa , University of Tsukuba
Shin'ichi Miura , University of Tsukuba
Taisuke Boku , University of Tsukuba
<p>The PCI Express Adaptive Communication Hub (Peach) is an eight-core communication system on chip with four PCI Express Revision 2.0 ports, each with four lanes. Peach realizes a high-performance, power-aware, highly dependable network that uses PCI Express not only for connecting peripheral devices but also as a communication link between computing nodes. This approach opens up new possibilities for a range of communications.</p>
PCI Express, network communications, multicore multiprocessor, single-chip multiprocessor, energy-aware system, dependability, Peach, PCI Express Adaptive Communication Hub
Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Toshihiro Hanawa, Shin'ichi Miura, Taisuke Boku, "Peach: A Multicore Communication System on Chip with PCI Express", IEEE Micro, vol.31, no. 6, pp. 39-50, Nov.-Dec. 2011, doi:10.1109/MM.2011.93
1. T. Hanawa et al, "PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express," Proc. IEEE/ACM Int'l Conf. Green Computing and Communications, 2010, doi:10.1109/CLUSTERWKSP.2010.561309.
2. S. Otani et al., "An 80Gb/s Dependable Communication SoC with PCI Express I/F and 8 CPUs," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 11), IEEE Press, 2011, pp. 266-268.
3. S. Otani et al., "An 80Gb/s Dependable Multicore Communication SoC with PCI Express I/F and Intelligent Interrupt Controller," Cool Chips XIV, IEEE Press, 2011, doi:10.1109/COOLCHIPS.2011.5890920.
4. S. Kaneko et al., "A 600MHz Single-Chip Multiprocessor with 4.8GB/s Internal Shared Pipelined Bus and 512kB Internal Memory," IEEE J. Solid-State Circuits, vol. 39, no. 1, 2004, pp. 184-193.
5. H. Kondo et al., "Design and Implementation of a Configurable Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors," IEEE J. Solid-State Circuits, vol. 43, no. 4, 2008, pp. 892-901.
6. PCI Express External Cabling Specification, Rev. 1.0, PCI-SIG, Jan. 2007; pcie_cabling1.0.
22 ms
(Ver 2.0)

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