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Issue No.06 - Nov.-Dec. (2011 vol.31)
pp: 29-38
Craig A. Court , Imperial College London
<p>Power gating reduces static power by either disabling whole units or dynamically resizing units to meet application demands. The Loop-Directed Mothballing technique lets users power gate execution units by recording utilization of individual units in loops, and by power gating units according to two utilization thresholds. LDM offers on average 10.3 percent total power savings with low performance loss.</p>
adaptable architectures, energy-aware systems, Loop-Directed Mothballing, power gating
Craig A. Court, "Loop-Directed Mothballing: Power Gating Execution Units Using Runtime Loop Analysis", IEEE Micro, vol.31, no. 6, pp. 29-38, Nov.-Dec. 2011, doi:10.1109/MM.2011.92
1. International Technology Roadmap for Semiconductors, 2010, http:/
2. K. Agarwal et al., "Power Gating with Multiple Sleep Modes," Proc. 7th Int'l Symp. Quality Electronic Design (ISQED 06), IEEE Press, 2006, pp. 633-637.
3. J.A. Butts and G.S. Sohi, "A Static Power Model for Architects," Proc. 33rd Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE Press, 2002, pp. 191-201.
4. S. Ghiasi, J. Casmira, and D. Grunwald, "Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption," Proc. Workshop Complexity Effective Design, 2000.
5. D. Ikebuchi et al., "Geyser-1: A MIPS R3000 CPU Core with Fine Grain Runtime Power Gating," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 09), IEEE Press, 2009, pp. 281-284.
6. A. Iyer and D. Marculescu, "Runtime Scaling of Microarchitecture Resources in a Processor for Energy Savings," Kool Chips Workshop, IEEE Press, 2000, pp. 82-85.
7. T.M. Jones et al., "Compiler Directed Early Register Release," Proc. 14th Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE Press, 2005, pp. 110-122.
8. R. Maro, Y. Bai, and R. Bahar, "Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors," Proc. 1st Int'l Workshop Power-Aware Computer Systems, Springer, 2001, pp. 97-111.
9. M. Powell et al., "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories," Proc. Int'l Symp. Low Power Electronics and Design, ACM Press, 2000, pp. 90-95.
10. A.R. Rawson, "PowerPC Reference Platform: Architectural Aspects of Power Management," white paper, IBM, Feb. 1995.
11. R. Rosner et al., "Power Awareness through Selective Dynamically Optimized Traces," Proc. 31st Ann. Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 162-173.
12. R. Gonzalez and M. Horowitz, "Energy Dissipation in General Purpose Microprocessors," IEEE J. Solid-State Circuits, vol. 31, no. 9, 2002, pp. 1277-1284.
13. D. Burger and T.M. Austin, "The SimpleScalar Tool Set, Version 2.0," ACM SIGARCH Computer Architecture News, vol. 25, no. 3, 1997, pp. 13-25.
14. S. Li et al., "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Many-Core Architectures," Proc. 42nd Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE Press, 2009, pp. 469-480.
15. 21264/EV68CB and 21264/EV68DC Hardware Reference Manual, Compaq, Shrewsbury, Mass., 2001.
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