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Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips
Nov.-Dec. 2011 (vol. 31 no. 6)
pp. 6-18
Nobuaki Ozaki, Keio University
Yoshihiro Yasuda, Keio University
Yoshiki Saito, Keio University
Daisuke Ikebuchi, Keio University
Masayuki Kimura, Keio University
Hideharu Amano, Keio University
Hiroshi Nakamura, University of Tokyo
Kimiyoshi Usami, Shibaura Institute of Technology
Mitaro Namiki, Tokyo University of Agriculture and Technology
Masaaki Kondo, University of Electro-Communications

Cool Mega-Array (CMA) is an energy-efficient reconfigurable accelerator for battery-driven mobile devices. It has a large processing-element array without memory elements for mapping an application's data-flow graph, a simple programmable microcontroller for data management, and data memory. Unlike coarse-grained dynamically reconfigurable processors, CMA reduces power consumption by switching hardware context and storing intermediate data in registers.

1. F.J. Veradas et al., "Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes," Proc. Int'l Conf. Field Programmable Logic and Applications (FPL 05), IEEE Press, 2005, pp. 106-111.
2. C. Ebeling et al., "RaPiD-Reconfigurable Pipelined Datapath," Proc. Int'l Workshop Field-Programmable Logic and Applications (FPL 96), Springer, 1996, pp. 126-135.
3. H. Schmit et al., "PipeRench: A Virtualized Programmable Datapath in 0.18-Micron Technology," Proc. IEEE Custom Integrated Circuits Conf., IEEE Press, 2002, pp. 63-66.
4. Y. Kurose et al., "A 90 nm Embedded Dram Single Chip LSI with a 3d Graphics, H.264 Codec Engine, and a Reconfigurable Processor," HotChips 16, 2004, http://www.hotchips.org/archives/hc16/3_Tue 8_HC16_Sess8_Pres1_bw.pdf.
5. M. Motomura, "STP Engine, A C-based Programmable HW Core Featuring Massively Parallel and Reconfigurable Processing Element Array: Its Architecture, Tool, and System Implications," COOL Chips XII, 2009.
6. Y. Saito et al., "A Real Chip Evaluation of MuCCRA-3: A Low Power Dynamically Reconfigurable Processor Array," Proc. 15th Asia and South Pacific Design Automation Conference (ASP-DAC 10), IEEE Press, 2010, pp. 377-378.
7. T. Sakurai et al., "Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, 1990, pp. 584-594.
8. V. Tunbunheng et al., "RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices," Proc. IEEE Int'l Conf. Field-Programmable Technology, IEEE Press, 2005, pp. 129-136.
9. V. Tunbunheng et al., "A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays," IEEE Trans. VLSI Systems, vol. E91-D, no.11, pp. 2655-2665.
10. Y. Yuyama et al., "A 45 nm 37.3GOPS/W Heterogeneous Multi-core SoC," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 10), IEEE Press, 2010, pp. 100-101.
11. F. Clermidy et al., "A 477 mW NoC-Based Digital Baseband for MIMO 4G SDR," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 10), IEEE Press, 2010, pp. 278-279.

Index Terms:
Cool Mega-Array, processing-element array, energy-efficient accelerator, CMA-1, CMA-2, reconfigurable accelerator
Citation:
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, "Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips," IEEE Micro, vol. 31, no. 6, pp. 6-18, Nov.-Dec. 2011, doi:10.1109/MM.2011.94
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