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This introduction to the special issue on Cool Chips discusses the state of low-power, high-speed chips and challenges facing researchers. It introduces five articles exploring different solutions to reducing power consumption and enhancing chip performance.
Low-power, high-speed chips ( cool chips) encompass a broad range of architectures, applications, methodologies, and usage models. These technologies are present in multimedia, digital consumer electronics, mobile computing, graphics, encryption, robotics, networking, and biometrics. They are based on multiprocessing, reconfigurable computing, dependable computing, and memory architectures. Cool software, which includes binary translators and compilers, is also emerging.
These technologies all aim to reduce power consumption and enhance chip performance. Regardless of their goals, all of industry has been challenged with developing optimal solutions—both hardware and software—for power optimization according to the required performance. In general, to migrate decades' worth of legacy approaches to low-power technology, researchers approach these optimal solutions from the perspective of starting from scratch.
With this in mind, we've been organizing annual Cool Chips conferences since 1998. We celebrated Cool Chips XIV in April 2011. Cool Chips, a sister conference to Hot Chips, focuses on all aspects of cool technologies. Approximately 150 individuals attend the conference each year. In addition to regular paper presentations, the conference includes keynote and invited talks, special topic sessions, and poster and panel discussions. To attract submissions from engineers working in industry, the program committee bases acceptance on a short abstract. The conference proceedings include only the short abstract with the final presentation rather than a set of long papers. All program committee members reviewed each of the 23 submissions for Cool Chips XIV and selected the 10 best on the basis of technical merit and innovation.
This special issue of IEEE Micro captures four contributions from among five submissions. In addition to these, we selected one article recommended from Cool Chips XIII. Reconfigurability was a major topic at Cool Chips XIV, and the articles we selected for this issue reflect this trend.
In "Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips," Nobuaki Ozaki et al. describe the Cool Mega-Array (CMA) chip series, a highly energy-efficient reconfigurable accelerator for battery-driven mobile devices. They realize a large reconfigurable processing-element (PE) array with flexible data-management instructions to avoid unnecessary PE reconfiguration, and they realize an 8 × 8 PE array with 24-bit data width using a 65-nm CMOS to achieve 2.72 giga operations per second (GOPS) per 11.2 mW—the most energy-efficient accelerator ever reported.
"High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors" by Tomoya Suzuki et al. describes a software-defined radio baseband processor supporting up to 600 Mbps for the next-generation wireless standards. It's estimated to realize low-power operations of 500 mW for an IEEE 802.11n 4 × 4 multiple input, multiple output (MIMO), 600-Mbps data stream and, within only 2.6 ms, fast runtime switching between multiple wireless standards, such as switching from wireless LAN to WiMax.
In "Loop-Directed Mothballing: Power Gating Execution Units Using Runtime Loop Analysis," Craig A. Court and Paul H.J. Kelly describe Loop-Directed Mothballing (LDM), a method to power gate execution units by recording utilization of individual units in loops and power gating units by thresholds. LDM realizes an average 10.3 percent total power reduction, as well as 10.3 percent average energy-delay product reduction with less performance degradation.
"Peach: A Multicore Communication System on Chip with PCI Express" by Sugako Otani et al. describes an eight-core communication system on chip (SoC) with four PCI Express Revision 2.0 x4 ports for a high-performance, power-aware, highly dependable network. It realizes 51.5 percent better power efficiency compared with available high-bandwidth interfaces.
In "Advanced Camera Technologies for Broadcasting," Hiroshi Shimamoto et al. describe three types of super camera technologies: a 8,000-pixel by 4,000-line high-resolution camera for a greater sensation of reality; a 1 million frames per second (fps) high-speed camera for scientific applications as well as various TV programs, including sports, nature, science, and education; and a 50× higher-sensitivity camera to extend beyond broadcasting to the fields of radiation diagnosis, especially for high-contrast images with low-dose radiation.
Low power, low energy, power efficiency, energy efficiency, power awareness, and energy awareness are still among the most important factors for any kind of chip design. To cope with this subject, not only devices and circuits, but also a wide variety of innovations, including architecture, algorithms, and software, are essential. The Cool Chips conference series will continue to cover all kinds of low-power and high-performance chips, and is looking for future contributions.
It has been a pleasure to put together this special issue on Cool Chips. We thank Editor in Chief Erik Altman for his support and guidance. We also thank Tadao Nakamura, advisory committee chair of Cool Chips 2011, and Hiroaki Kobayashi, organizing committee chair, for their help in arranging this special issue. The issue would not have been possible without their help.
is an associate professor in the VLSI Design and Education Center at the University of Tokyo. His research interests include high-performance, low-power, and reliable digital circuit and smart image sensor design. Ikeda has a PhD in electrical engineering from the University of Tokyo. He's a program committee co-chair of the Cool Chips conference series and a program committee member of the International Solid-State Circuits Conference, VLSI Circuits Symposium, Asian Solid-State Circuits Conference, International Symposium on Quality Electronic Design, and International Conference on Field Programmable Technology.
is a chief professional in the System Core Development Division of Renesas Electronics. His research interests include architecture and microarchitecture of low-power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from the University of Tokyo. He's a program committee co-chair of the Cool Chips conference series, a program committee member of the VLSI Circuits Symposium and Asian Solid-State Circuits Conference, and the chairman of Microprocessor Technical Committee and Multi-/Many-core Application Research Committee of Japan Electronics and Information Technology Industries Association. He's a member of IEEE and the Institute of Electronics, Information, and Communication Engineers.