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Physical Synthesis with Clock-Network Optimization for Large Systems on Chips
July/August 2011 (vol. 31 no. 4)
pp. 51-62
David Papa, Broadway Technology
Cliff Sze, IBM Austin Research Laboratory
Zhuo Li, IBM Austin Research Laboratory
Gi-Joon Nam, IBM Austin Research Laboratory
Charles Alpert, IBM Austin Research Laboratory
Igor L. Markov, University of Michigan, Ann Arbor

In traditional physical-synthesis methodologies, the placement of flip-flops and latches is problematic, especially for large systems on chips. A next-generation electronic-design-automation methodology improves timing closure through clock-network synthesis and placement of flip-flops and latches to avoid timing disruptions or immediately recover from them. When evaluated on large CPU designs, the methodology saw double-digit improvements in timing, wirelength, and area versus current technology.

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1. D. Chinnery and K. Keutzer, Closing the Gap between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design, Kluwer Academic Publishers, 2002.
2. D. Chinnery and K. Keutzer, Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design, Kluwer Academic Publishers, 2010.
3. Y.-H. Chan et al., "Physical Synthesis Methodology for High Performance Microprocessors," Proc. 40th Ann. Design Automation Conf., ACM Press, 2003, pp. 696-701.
4. Y. Cheon et al., "Power-Aware Placement," Proc. 42nd Design Automation Conf., ACM Press, 2005, pp. 795-800.
5. Y.-T. Chang et al., "Post-Placement Power Optimization with Multi-bit Flip-Flops," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, IEEE Press, 2010, pp. 218-223.
1. Y.-H. Chan et al., "Physical Synthesis Methodology for High Performance Microprocessors," Proc. 40th Ann. Design Automation Conf., ACM Press, 2003, pp. 696-701.
2. C.J. Alpert et al., "Techniques for Fast Physical Synthesis," Proc. IEEE, vol. 95, no. 3, 2007, pp. 573-599.
3. D. Chinnery and K. Keutzer, Closing the Gap between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design, Kluwer, 2002.
4. D. Chinnery and K. Keutzer, Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design, Kluwer, 2010.
5. Y.-T. Chang et al., "Post-Placement Power Optimization with Multi-Bit Flip-Flops," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, IEEE Press, 2010, pp. 218-223.
6. Y. Cheon et al., "Power-Aware Placement," Proc. 42nd Design Automation Conf., ACM Press, 2005, pp. 795-800.

Index Terms:
physical synthesis, systems on chips
Citation:
David Papa, Natarajan Viswanathan, Cliff Sze, Zhuo Li, Gi-Joon Nam, Charles Alpert, Igor L. Markov, "Physical Synthesis with Clock-Network Optimization for Large Systems on Chips," IEEE Micro, vol. 31, no. 4, pp. 51-62, July-Aug. 2011, doi:10.1109/MM.2011.41
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