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Issue No.04 - July/August (2011 vol.31)
pp: 51-62
David Papa , Broadway Technology
Cliff Sze , IBM Austin Research Laboratory
Zhuo Li , IBM Austin Research Laboratory
Gi-Joon Nam , IBM Austin Research Laboratory
Charles Alpert , IBM Austin Research Laboratory
Igor L. Markov , University of Michigan, Ann Arbor
ABSTRACT
<p>In traditional physical-synthesis methodologies, the placement of flip-flops and latches is problematic, especially for large systems on chips. A next-generation electronic-design-automation methodology improves timing closure through clock-network synthesis and placement of flip-flops and latches to avoid timing disruptions or immediately recover from them. When evaluated on large CPU designs, the methodology saw double-digit improvements in timing, wirelength, and area versus current technology.</p>
INDEX TERMS
physical synthesis, systems on chips
CITATION
David Papa, Natarajan Viswanathan, Cliff Sze, Zhuo Li, Gi-Joon Nam, Charles Alpert, Igor L. Markov, "Physical Synthesis with Clock-Network Optimization for Large Systems on Chips", IEEE Micro, vol.31, no. 4, pp. 51-62, July/August 2011, doi:10.1109/MM.2011.41
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