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Big Chips
July/August 2011 (vol. 31 no. 4)
pp. 3-5
| ASCII Text | x | ||
| Andrew B. Kahng, Vijayalakshmi Srinivasan, "Big Chips," IEEE Micro, vol. 31, no. 4, pp. 3-5, July/August, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2011.72, author = {Andrew B. Kahng and Vijayalakshmi Srinivasan}, title = {Big Chips}, journal ={IEEE Micro}, volume = {31}, number = {4}, issn = {0272-1732}, year = {2011}, pages = {3-5}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2011.72}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Big Chips IS - 4 SN - 0272-1732 SP3 EP5 EPD - 3-5 A1 - Andrew B. Kahng, A1 - Vijayalakshmi Srinivasan, PY - 2011 KW - Big chips KW - dark silicon KW - 3D integration KW - network scalability KW - field-programmable gate arrays KW - thermal design power KW - large-scale designs KW - physical synthesis KW - dynamic voltage and frequency scaling KW - clock network synthesis KW - hardware accelerators VL - 31 JA - IEEE Micro ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2011.72
This introduction to the special issue provides a snapshot and a sampling of current activity related to the architecture and design of big chips.
Index Terms:
Big chips, dark silicon, 3D integration, network scalability, field-programmable gate arrays, thermal design power, large-scale designs, physical synthesis, dynamic voltage and frequency scaling, clock network synthesis, hardware accelerators
Citation:
Andrew B. Kahng, Vijayalakshmi Srinivasan, "Big Chips," IEEE Micro, vol. 31, no. 4, pp. 3-5, July-Aug. 2011, doi:10.1109/MM.2011.72
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