|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Wei Huang, Malcolm Allen-Ware, John B. Carter, Mircea R. Stan, Kevin Skadron, Edmund Cheng, "Temperature-Aware Architecture: Lessons and Opportunities," IEEE Micro, vol. 31, no. 3, pp. 82-86, May/June, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2011.60, author = {Wei Huang and Malcolm Allen-Ware and John B. Carter and Mircea R. Stan and Kevin Skadron and Edmund Cheng}, title = {Temperature-Aware Architecture: Lessons and Opportunities}, journal ={IEEE Micro}, volume = {31}, number = {3}, issn = {0272-1732}, year = {2011}, pages = {82-86}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2011.60}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Temperature-Aware Architecture: Lessons and Opportunities IS - 3 SN - 0272-1732 SP82 EP86 EPD - 82-86 A1 - Wei Huang, A1 - Malcolm Allen-Ware, A1 - John B. Carter, A1 - Mircea R. Stan, A1 - Kevin Skadron, A1 - Edmund Cheng, PY - 2011 KW - Temperature-aware design KW - server system KW - thermal model KW - heat transfer KW - cooling solution KW - hotspots KW - temperature sensors VL - 31 JA - IEEE Micro ER - | |||
Managing temperature is an important concern in modern processor and other microelectronic chips. This column explores recent lessons and future challenges in temperature-aware design.
1. P. Dadvar and K. Skadron, "Potential Thermal Security Risks," Proc. 21st Ann. IEEE Semiconductor Thermal Measurement and Management Symp., IEEE Press, 2005, pp. 229-234.
2. K. Skadron et al., "Temperature-Aware Microarchitecture," Proc. 30th Ann. Int'l Symp. Computer Architecture, ACM Press, 2003, pp. 2-13.
3. T. Heath et al., "Mercury and Freon: Temperature Emulation and Management for Server Systems," Proc. 12th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, 2006, pp. 106-116.
4. W. Huang et al., "The Need for a Full-Chip and Package Thermal Model for Thermally Optimized IC Designs," Proc. 2005 Int'l Symp. Low Power Electronics and Design, ACM Press, 2005, pp. 245-250.
5. W. Huang et al., "Accurate, Pre-RTL Temperature-Aware Processor Design using a Parameterized, Geometric Thermal Model," IEEE Trans. Computers, vol. 57, no. 9, 2008, pp. 1277-1288.
6. Y. Yang et al., "ISAC: Integrated Space and Time Adaptive Chip-Package Thermal Analysis," IEEE Trans. Computer-Aided Design, vol. 26, no. 1, 2007, pp. 86-99.
7. Y. Li et al., "Performance, Energy, and Thermal Considerations for SMT and CMP Architectures," Proc. 11th Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, 2005, pp. 71-82.
8. W. Huang et al., "Exploring the Thermal Impact on Many-Core Processor Performance," Proc. 26th Ann. IEEE Semiconductor Thermal Measurement and Management Symp., IEEE Press, 2010, pp. 191-197.
9. C. Green, A. Fedorov, and Y. Joshi, "Fluid-to-Fluid Spot-to-Spreader (F2/S2) Hybrid Heat Sink for Integrated Chip-Level and Hot Spot-Level Thermal Management," ASME J. Electronic Packaging, vol. 131, no. 6, 2009, doi:10.1115/1.3104029.
10. W. Huang et al., "Interaction of Scaling Trends in Processor Architecture and Cooling," Proc. 26th Ann. IEEE Semiconductor Thermal Measurement and Management Symp., IEEE Press, 2010, pp. 198-204.
11. T. Brunschwiler et al., "Forced Convective Interlayer Cooling Potential in Vertically Integrated Packages," Proc. IEEE/ASME 10th Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems, IEEE Press, 2008, pp. 1114-1125.
12. D. Shin et al., "Energy-Optimal Dynamic Thermal Management for Green Computing," Proc. 2009 Int'l Conf. Computer-Aided Design, ACM Press, 2009, pp. 652-657.
13. Gradient DA, "Case Study," http://www.gradient-da.com/resourcescase-study2.php .
14. J. Kong, S.W. Chung, and K. Skadron, "Recent Thermal Management Techniques for Microprocessors," to be published in ACM Computing Surveys, 2011.
15. A. Coskun et al., "Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SOCS," IEEE Trans. VLSI, vol. 16, no. 9, 2008, pp. 1127-1140.
16. E. Humenay, D. Tarjan, and K. Skadron, "Impact of Process Variations on Multicore Performance Symmetry," Proc. Conf. Design, Automation, and Test in Europe, EDA Consortium, 2007, pp. 1653-1658.
17. A.K. Coskun, T.S. Rosing, and K.C. Gross, "Proactive Temperature Balancing for Low Cost Thermal Management in MPSOCS," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, IEEE Press, 2008, pp. 250-257.
18. S. Sharifi and T. Simunic Rosing, "Accurate Direct and Indirect On-chip Temperature Sensing for Efficient Dynamic Thermal Management," IEEE Trans. Computer-Aided Design, vol. 29, no. 10, 2010, pp. 1586-1599.
19. Z. Hassan et al., "Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits," IEEE Trans. Computer-Aided Design, vol. 28, no. 6, 2009, pp. 860-873.
20. H.F. Hamann et al., "Uncovering Energy-Efficiency Opportunities in Data Centers," IBM J. Research and Development, vol. 53, no. 3, 2009, pp. 10:1-10:12.