The Community for Technology Leaders
RSS Icon
Issue No.02 - March/April (2011 vol.31)
pp: 60-75
<p>Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power and performance goals. These innovative features include per-core frequency scaling with available autonomic frequency control, per-chip automated voltage slewing, power consumption estimation, and hardware instrumentation assist.</p>
Power7, power management, energy efficiency, EnergyScale, frequency scaling, voltage slewing, performance, hardware
Michael Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, Jose A. Tierno, Pradip Bose, Alper Buyuktosunoglu, "Introducing the Adaptive Energy Management Features of the Power7 Chip", IEEE Micro, vol.31, no. 2, pp. 60-75, March/April 2011, doi:10.1109/MM.2011.29
1. M. Broyles et al., "IBM EnergyScale for Power7 Processor-Based Systems," white paper, IBM, Aug. 2010.
2. H.-Y. McCreary et al., "EnergyScale for IBM Power6 Microprocessor-Based Systems," IBM J. Research and Development, vol. 51, no. 6, 2007, pp. 775-786.
3. M.S. Floyd et al., "System Power Management Support in the IBM Power6 Microprocessor," IBM J. Research and Development, vol. 51, no. 6, 2007, pp. 733-746.
4. M. Yoshida and D.W. Boerstler, Thermal Sensing Circuit Using Band Gap Voltage Reference Generators without Trimming Circuitry, US patent 7,789,558, to Toshiba and IBM, Patent and Trademark Office, 2010.
5. T.H. Lee, M.G. Johnson, and M.P. Crowley, Temperature Sensor Integral with Microprocessor and Methods of Using Same, US patent 5,961,215, to Advanced Micro Devices, Patent and Trademark Office, 1999.
6. J.G. O'Dwyer, Apparatus and Method for Temperature Measurement Using a Band Gap Voltage Reference, US patent 7,225,099, to Xilinx, Patent and Trademark Office, 2007.
7. A. Drake et al., "A Distributed Critical Path Timing Monitor for a 65-nm High-Performance Microprocessor," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2007, doi:10.1109/ISSCC.2007.373462.
8. J. Dorsey et al., "An Integrated Quad-Core Opteron Processor," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2007, doi:10.1109/ISSCC.2007.373608.
9. J.A. Tierno, A.V. Rylyakov, and D.J. Friedman, "A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI," IEEE J. Solid-State Circuits, vol. 43, no. 1, 2008, pp. 42-51.
10. C. Isci and M. Martonosi, "Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data," Proc. 36th Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE CS Press, 2003, doi:10.1109/MICRO.2003.1253186.
11. R. Jotwani et al., "An x86-64 Core Implemented in 32nm SOI CMOS," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2010, doi:10.1109/ISSCC.2010.5434076.
12. B. Stackhouse et al., "A 65-nm 2-Billion Transistor Quad-Core Itanium Processor," IEEE J. Solid-State Circuits, vol. 44, no. 1, 2009, pp. 18-31.
13. SPECpower_ssj2008, version 1.10, Standard Performance Evaluation Corp., Warrenton, VA, 2010.
14. IBM Power 750 Express Server, IBM Systems and Technology Group, Somers, NY, 2010.
15. K. Choi, R. Soma, and M. Pedram, "Dynamic Voltage and Frequency Scaling Based on Workload Decomposition," Proc. 2004 Int'l Symp. Low Power Electronics and Design, ACM Press, 2004, pp. 174-179.
16. G. Semeraro et al., "Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling," Proc. 8th Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, 2002, pp. 29-40.
17. N. Abou Ghazaleh et al., "Integrated CPU and L2 Cache Frequency/Voltage Scaling Using Supervised Learning," Proc. 2007 ACM SIGPLAN/SIGBED Conf. Languages, Compilers, and Tools for Embedded Systems, ACM Press, 2007, p. 41-50.
17 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool