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| Brad Burgess, Brad Cohen, Marvin Denman, Jim Dundas, David Kaplan, Jeff Rupley, "Bobcat: AMD's Low-Power x86 Processor," IEEE Micro, vol. 31, no. 2, pp. 16-25, March/April, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2011.2, author = {Brad Burgess and Brad Cohen and Marvin Denman and Jim Dundas and David Kaplan and Jeff Rupley}, title = {Bobcat: AMD's Low-Power x86 Processor}, journal ={IEEE Micro}, volume = {31}, number = {2}, issn = {0272-1732}, year = {2011}, pages = {16-25}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2011.2}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Bobcat: AMD's Low-Power x86 Processor IS - 2 SN - 0272-1732 SP16 EP25 EPD - 16-25 A1 - Brad Burgess, A1 - Brad Cohen, A1 - Marvin Denman, A1 - Jim Dundas, A1 - David Kaplan, A1 - Jeff Rupley, PY - 2011 KW - microprocessor KW - low power KW - microarchitecture VL - 31 JA - IEEE Micro ER - | |||
Bobcat is an AMD processor core designed for the low-power, mobile, lower-end desktop x86 markets. This core should push current technology in many areas while balancing performance, area, and power consumption. Bobcat supports the 64-bit AMD64 ISA, various SIMD extensions, and a full virtual machine implementation. Bobcat is featured on the AMD Fusion processor family roadmap alongside vector-based parallel processing units in accelerated processing unit configurations.
1. C.N. Keltcher et al., "The AMD Opteron Processor for Multiprocessor Servers," IEEE Micro, vol. 23, no. 2, 2003, pp. 66-76.
2. D. Tan, C.E. Lemonds, and M.J. Schulte, "Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support," IEEE Trans. Computers, vol. 58, no. 2, 2009, pp. 175-187.