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Bulldozer: An Approach to Multithreaded Compute Performance
March/April 2011 (vol. 31 no. 2)
pp. 6-15
Michael Butler, Advanced Micro Devices
Leslie Barnes, Advanced Micro Devices
Debjit Das Sarma, Advanced Micro Devices
Bob Gelinas, Advanced Micro Devices

AMD's Bulldozer module represents a new direction in microarchitecture and includes a number of firsts for AMD, including AMD's multithreaded x86 processor, implementation of a shared Level 2 cache, and x86 processor to incorporate floating-point multiply-accumulate (FMAC). This article discusses the module's multithreading architecture, power-efficient microarchitecture, and subblocks, including the various microarchitectural latencies, bandwidths, and structure sizes.

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Index Terms:
Microprocessors, microcomputers, microarchitecture implementation considerations, processor architectures, Bulldozer
Citation:
Michael Butler, Leslie Barnes, Debjit Das Sarma, Bob Gelinas, "Bulldozer: An Approach to Multithreaded Compute Performance," IEEE Micro, vol. 31, no. 2, pp. 6-15, March-April 2011, doi:10.1109/MM.2011.23
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