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Address Translation Aware Memory Consistency
January/February 2011 (vol. 31 no. 1)
pp. 109-118
Bogdan F. Romanescu, Duke University
Alvin R. Lebeck, Duke University
Daniel J. Sorin, Duke University

Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need.

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Index Terms:
Memory consistency, virtual memory, address translation, dynamic verification
Citation:
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, "Address Translation Aware Memory Consistency," IEEE Micro, vol. 31, no. 1, pp. 109-118, Jan.-Feb. 2011, doi:10.1109/MM.2010.99
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