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| Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravi Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian, "CHOP: Integrating DRAM Caches for CMP Server Platforms," IEEE Micro, vol. 31, no. 1, pp. 99-108, January/February, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2010.100, author = {Xiaowei Jiang and Niti Madan and Li Zhao and Mike Upton and Ravi Iyer and Srihari Makineni and Donald Newell and Yan Solihin and Rajeev Balasubramonian}, title = {CHOP: Integrating DRAM Caches for CMP Server Platforms}, journal ={IEEE Micro}, volume = {31}, number = {1}, issn = {0272-1732}, year = {2011}, pages = {99-108}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2010.100}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - CHOP: Integrating DRAM Caches for CMP Server Platforms IS - 1 SN - 0272-1732 SP99 EP108 EPD - 99-108 A1 - Xiaowei Jiang, A1 - Niti Madan, A1 - Li Zhao, A1 - Mike Upton, A1 - Ravi Iyer, A1 - Srihari Makineni, A1 - Donald Newell, A1 - Yan Solihin, A1 - Rajeev Balasubramonian, PY - 2011 KW - CHOP KW - hot pages KW - cache memories KW - filter cache KW - DRAM KW - emerging technologies KW - memory hierarchy KW - hardware VL - 31 JA - IEEE Micro ER - | |||
Integrating large DRAM caches is a promising way to address the memory bandwidth wall issue in the many-core era. However, organizing and implementing a large DRAM cache imposes a trade-off between tag space overhead and memory bandwidth consumption. CHOP (Caching Hot Pages) addresses this trade-off through three filter-based DRAM-caching techniques.
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