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Issue No.01 - January/February (2011 vol.31)
pp: 99-108
Niti Madan , IBM Thomas J. Watson Research Center
Li Zhao , Intel
Mike Upton , Intel
Ravi Iyer , Intel
Yan Solihin , North Carolina State University
Rajeev Balasubramonian , University of Utah
<p>Integrating large DRAM caches is a promising way to address the memory bandwidth wall issue in the many-core era. However, organizing and implementing a large DRAM cache imposes a trade-off between tag space overhead and memory bandwidth consumption. CHOP (Caching Hot Pages) addresses this trade-off through three filter-based DRAM-caching techniques.</p>
CHOP, hot pages, cache memories, filter cache, DRAM, emerging technologies, memory hierarchy, hardware
Niti Madan, Li Zhao, Mike Upton, Ravi Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian, "CHOP: Integrating DRAM Caches for CMP Server Platforms", IEEE Micro, vol.31, no. 1, pp. 99-108, January/February 2011, doi:10.1109/MM.2010.100
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