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Issue No.01 - January/February (2011 vol.31)
pp: 90-98
Jeffrey Stuecheli , University of Texas at Austin
Dimitris Kaseridis , University of Texas at Austin
Lizy K. John , University of Texas at Austin
David Daly , IBM Thomas J. Watson Research Center
Hillery C. Hunter , IBM Thomas J. Watson Research Center
<p>To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance.</p>
Memory, DRAM, cache, memory bandwidth, cache write-back, memory scheduling, last-level cache, cache replacement, DRAM page-mode, DRAM parameters
Jeffrey Stuecheli, Dimitris Kaseridis, Lizy K. John, David Daly, Hillery C. Hunter, "Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue", IEEE Micro, vol.31, no. 1, pp. 90-98, January/February 2011, doi:10.1109/MM.2010.102
1. R. Kalla, B. Sinharoy, and J.M. Tendler, "IBM Power5 Chip: A Dual-Core Multithreaded Processor," IEEE Micro, vol. 24, no. 2, 2004, pp. 40-47.
2. H. Lee, G. Tyson, and M. Farrens, "Eager Writeback—A Technique for Improving Bandwidth Utilization," Proc. Int'l Symp. Micoarchitecture (MICRO), ACM Press, 2000, pp. 11-21.
3. M. Valero, T. Lang, and E. Ayguadé, "Conflict-Free Access of Vectors with Power-of-Two Strides," Proc. Int'l Conf. Supercomputing, ACM Press, 1992, pp. 149-156.
4. Jeffrey Stuecheli et al., "The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies," Proc. 37th Ann. Int'l Symp. Computer Architecture (ISCA 10), ACM Press, 2010, pp. 72-82.
5. M. Martin et al., "Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset," Computer Architecture News (CAN), Nov. 2005, pp. 92-99.
6. S. Rixner et al., "Memory Access Scheduling," Proc. Int'l Symp. Computer Architecture (ISCA 27), IEEE CS Press, 2000, pp. 128-138.
7. Micron Technologies, DDR3 SDRAM System-Power Calculator, revision 0.1, Mar. 2007.
24 ms
(Ver 2.0)

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