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Cohesion: An Adaptive Hybrid Memory Model for Accelerators
January/February 2011 (vol. 31 no. 1)
pp. 42-55
John H. Kelm, University of Illinois at Urbana-Champaign
Daniel R. Johnson, University of Illinois at Urbana-Champaign
William Tuohy, University of Illinois at Urbana-Champaign
Steven S. Lumetta, University of Illinois at Urbana-Champaign
Sanjay J. Patel, University of Illinois at Urbana-Champaign

Cohesion is a hybrid memory model that enables fine-grained temporal data reassignment between hardware- and software-managed coherence domains, allowing systems to support both. Cohesion can dynamically adapt to the sharing needs of both applications and runtimes requiring neither copy operations nor multiple address spaces.

1. J.H. Kelm et al., "Cohesion: A Hybrid Memory Model for Accelerators," Proc. 37th Ann. Int'l Symp. Computer Architecture, ACM Press, 2010, pp. 429-440.
2. S.V. Adve et al., "Comparison of Hardware and Software Cache Coherence Schemes," Sigarch Computer Architecture News, vol. 19, no. 3, 1991, pp. 298-308.
3. J.K. Bennett, J.B. Carter, and W. Zwaenepoel, "Munin: Distributed Shared Memory Based On Type-Specific Memory Coherence," Proc. 2nd ACM Sigplan Symp. Principles & Practice of Parallel Programming, ACM Press, 1990, pp. 168-176.
4. M.D. Hill et al., "Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors," ACM Trans. Computer Systems, vol. 11, no. 4, 1993, pp. 300-318.
5. J.H. Kelm et al., "A Task-Centric Memory Model for Scalable Accelerator Architectures," Proc. 18th Int'l Conf. Parallel Architectures and Compilation Techniques (Pact 09), IEEE CS Press, 2009, pp. 77-87.
6. L.M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Trans. Computers, vol. 27, no. 12, 1978, pp. 1112-1118.
7. L.A. Barroso et al., "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing," Proc. 27th Ann. Int'l Symp. Computer Architecture, ACM Press, 2000, pp. 282-293.
8. M. Frigo, C.E. Leiserson, and K.H. Randall, "The Implementation of the Cilk-5 Multithreaded Language," ACM Sigplan Notices, vol. 33, no. 5, 1998, pp. 212-223.
9. J. Reinders, Intel Threading Building Blocks: Outfitting C++ for Multi-Core Processor Parallelism, O'Reilly, 2007.
10. M. Gschwind, "Chip Multiprocessing and the Cell Broadband Engine," Proc. 3rd Conf. Computing Frontiers, ACM, 2006, pp. 1-8, doi:10.1145/1128022.1128023.
11. J.H. Kelm et al., "Rigel: An Architecture and Scalable Programming Interface for a 1000-Core Accelerator," Proc. 36th Ann. Int'l Symp. Computer Architecture, ACM Press, 2009, pp. 140-151.
1. C. Amza et al., "Treadmarks: Shared Memory Computing on Networks of Workstations," Computer, vol. 29, no. 2, 1996, pp. 18-28.
2. D.J. Scales, K. Gharachorloo, and C.A. Thekkath, "Shasta: A Low Overhead, Software-Only Approach for Fine-Grain Shared Memory," Proc. 7th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, 1996, pp. 174-185.
3. M.D. Hill et al., "Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors," ACM Trans. Computer Systems, vol. 11, no. 4, 1993, pp. 300-318.
4. D. Chaiken, J. Kubiatowicz, and A. Agarwal, "LimitLESS Directories: A Scalable Cache Coherence Scheme," Proc. 4th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, 1991, pp. 224–234.
5. J. Kuskin et al., "The Stanford Flash Multiprocessor," Proc. 21st Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 1994, pp. 302-313.
6. J.K. Bennett, J.B. Carter, and W. Zwaenepoel, "Munin: Distributed Shared Memory Based on Type-Specific Memory Coherence," Proc. 2nd ACM Sigplan Symp. Principles & Practice of Parallel Programming, ACM Press, 1990, pp. 168-176.
7. J. De Souza and L.V. Kal, "MSA: Multiphase Specifically Shared Arrays," Proc. 17th Int'l Workshop Languages and Compilers for Parallel Computing, LNCS 3602, Springer, 2005, pp. 268-282.
8. B. Saha et al., "Programming Model for a Heterogeneous x86 Platform," Proc. 2009 ACM Sigplan Conf. Programming Language Design and Implementation, ACM Press, 2009, pp. 431-440.

Index Terms:
Accelerator, computer architecture, cache coherence
Citation:
John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel, "Cohesion: An Adaptive Hybrid Memory Model for Accelerators," IEEE Micro, vol. 31, no. 1, pp. 42-55, Jan.-Feb. 2011, doi:10.1109/MM.2011.8
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