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| Ofer Shacham, Omid Azizi, Megan Wachs, Wajahat Qadeer, Zain Asgar, Kyle Keley, John P. Stevenson, Stephen Richardson, Mark Horowitz, Benjamin Lee, Alex Solomatnikov, Amin Firoozshahian, "Rethinking Digital Design: Why Design Must Change," IEEE Micro, vol. 30, no. 6, pp. 9-24, November/December, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2010.81, author = {Ofer Shacham and Omid Azizi and Megan Wachs and Wajahat Qadeer and Zain Asgar and Kyle Keley and John P. Stevenson and Stephen Richardson and Mark Horowitz and Benjamin Lee and Alex Solomatnikov and Amin Firoozshahian}, title = {Rethinking Digital Design: Why Design Must Change}, journal ={IEEE Micro}, volume = {30}, number = {6}, issn = {0272-1732}, year = {2010}, pages = {9-24}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2010.81}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Rethinking Digital Design: Why Design Must Change IS - 6 SN - 0272-1732 SP9 EP24 EPD - 9-24 A1 - Ofer Shacham, A1 - Omid Azizi, A1 - Megan Wachs, A1 - Wajahat Qadeer, A1 - Zain Asgar, A1 - Kyle Keley, A1 - John P. Stevenson, A1 - Stephen Richardson, A1 - Mark Horowitz, A1 - Benjamin Lee, A1 - Alex Solomatnikov, A1 - Amin Firoozshahian, PY - 2010 KW - Moore's Law KW - Dennard scaling KW - CMOS KW - ASIC KW - system on chip KW - chip multiprocessor KW - power efficiency KW - hardware generation KW - chip generator KW - hardware optimization KW - design methodology KW - RTL verification KW - H.264 VL - 30 JA - IEEE Micro ER - | |||
Because of technology scaling, power dissipation is today's major performance limiter. Moreover, the traditional way to achieve power efficiency, application-specific designs, is prohibitively expensive. These power and cost issues necessitate rethinking digital design. To reduce design costs, we need to stop building chip instances, and start making chip generators instead. Domain-specific chip generators are templates that codify designer knowledge and design trade-offs to create different application-optimized chips.
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