This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Rethinking Digital Design: Why Design Must Change
November/December 2010 (vol. 30 no. 6)
pp. 9-24
Ofer Shacham, Stanford University
Omid Azizi, Stanford University
Megan Wachs, Stanford University
Wajahat Qadeer, Stanford University
Zain Asgar, Stanford University
Kyle Keley, Stanford University
John P. Stevenson, Stanford University
Stephen Richardson, Stanford University
Mark Horowitz, Stanford University
Benjamin Lee, Duke University
Alex Solomatnikov, Hicamp Systems
Amin Firoozshahian, Hicamp Systems

Because of technology scaling, power dissipation is today's major performance limiter. Moreover, the traditional way to achieve power efficiency, application-specific designs, is prohibitively expensive. These power and cost issues necessitate rethinking digital design. To reduce design costs, we need to stop building chip instances, and start making chip generators instead. Domain-specific chip generators are templates that codify designer knowledge and design trade-offs to create different application-optimized chips.

1. A. Sangiovanni-Vincentelli and G. Martin, "Platform-Based Design and Software Design Methodology for Embedded Systems," IEEE Design & Test, vol. 18, no. 6, 2001, pp. 23-33.
2. G.E. Moore, "Cramming More Components onto Integrated Circuits," Electronics, vol. 38, no. 8, 1965, pp. 114-117; http://download.intel.com/research.silicon moorespaper.pdf.
3. R.H. Dennard et al., "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," Proc. IEEE J. Solid-State Circuits, vol. 9, no. 5, 1974, pp. 256-268.
4. "SPEC CPU2006 Results," Standard Performance Evaluation Corp., 2006; http://www.spec.org/cpu2006results.
5. P. Hanrahan, "Keynote: Why Are Graphics Systems So Fast?" Proc. 18th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 09), IEEE CS Press, 2009, p. xv.
6. J. Balfour et al., "An Energy-Efficient Processor Architecture for Embedded Systems," Computer Architecture Letters, vol. 7, no. 1, 2008, pp. 29-32.
7. R.E. Collett, "How to Address Today's Growing System Complexity," 13th Ann. Design, Automation and Test in Europe Conf. (DATE 10), executive session, IEEE CS, 2010.
8. D. Grose, "From Contract to Collaboration Delivering a New Approach to Foundry," keynote, 47th Design Automation Conf. (DAC 10), ACM, 2010; http://www2.dac.com/App_Content/filesGF_Doug_Grose_DAC.pdf .
9. A. Solomatnikov et al., "Using a Configurable Processor Generator for Computer Architecture Prototyping," Proc. 42nd Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro 09), ACM Press, 2009, pp. 358-369.
10. T. Weigand et al., "Overview of the H.264/AVC Video Coding Standard," IEEE Trans. Circuits and Systems for Video Technology, vol. 13, no. 7, 2003, pp. 560-576.
11. K. Kuah, "Motion Estimation with Intel Streaming SIMD Extensions 4 (Intel SSE4)," Intel, 29 Oct. 2008; http://software.intel.com/en-us/articles motion-estimation-with-intel-streaming-simd-extensions-4-intel-sse4 .
12. R. Hameed et al., "Understanding Sources of Inefficiency in General-Purpose Chips," Proc. 37th Ann. Int'l Symp. Computer Architecture (ISCA 10), ACM Press, 2010, pp. 37-47.
13. H. Li et al., "Accelerated Motion Estimation of H.264 on Imagine Stream Processor," Proc. Image Analysis and Recognition, LNCS 3656, Springer, 2005, pp. 367-374.
14. C. Johnson et al., "A Wire-Speed Power Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 10), IEEE Press, 2010, pp. 14-16.
15. B.C. Lee and D.M. Brooks, "Accurate and Efficient Regression Modeling for Microarchitectural Performance and Power Prediction," ACM SIGARCH Computer Architecture News, vol. 34, no. 5, 2006, pp. 185-194.
16. O. Azizi et al., "Energy-Performance Tradeoffs in Processor Architecture and Circuit Design: A Marginal Cost Analysis," Proc. 37th Ann. Int'l Symp. Computer Architecture (ISCA 10), ACM Press, 2010, pp. 26-36.
17. Y. Naveh et al., "Constraint-Based Random Stimuli Generation for Hardware Verification," Proc. 18th Conf. Innovative Applications of Artificial Intelligence (IAAI 06), AAAI Press, 2006, pp. 1720-1727.
18. S. Hangal et al., "TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model," Proc. 31st Ann. Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 114-123.
19. O. Shacham et al., "Verification of Chip Multiprocessor Memory Systems Using A Relaxed Scoreboard," Proc. 41st IEEE/ACM Int'l Symp. Microarchitecture (Micro 08), IEEE CS Press, 2008, pp. 294-305.
1. K. Mai et al., "Smart Memories: A Modular Reconfigurable Architecture," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA 00), ACM Press, 2000, pp. 161-171.
2. A. Solomatnikov, "Polymorphic Chip Multiprocessor Architecture," doctoral dissertation, Dept. of Electrical Eng., Stanford Univ., 2008.
3. R.E. Gonzalez, "Xtensa: A Configurable and Extensible Processor," IEEE Micro, vol. 20, no. 2, 2000, pp. 60-70.
4. K. Mai et al., "Architecture and Circuit Techniques for a 1.1-GHz 16-kb Reconfigurable Memory in 0.18-μm CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 1, 2005, pp. 261-275.
5. A. Firoozshahian et al., "A Memory System Design Framework: Creating Smart Memories," Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA 09), ACM Press, 2009, pp. 406-417.

Index Terms:
Moore's Law, Dennard scaling, CMOS, ASIC, system on chip, chip multiprocessor, power efficiency, hardware generation, chip generator, hardware optimization, design methodology, RTL verification, H.264
Citation:
Ofer Shacham, Omid Azizi, Megan Wachs, Wajahat Qadeer, Zain Asgar, Kyle Keley, John P. Stevenson, Stephen Richardson, Mark Horowitz, Benjamin Lee, Alex Solomatnikov, Amin Firoozshahian, "Rethinking Digital Design: Why Design Must Change," IEEE Micro, vol. 30, no. 6, pp. 9-24, Nov.-Dec. 2010, doi:10.1109/MM.2010.81
Usage of this product signifies your acceptance of the Terms of Use.