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Issue No.05 - September/October (2010 vol.30)
pp: 76-87
Ulrich Drepper , Red Hat
Pascal Felber , University of Neuchatel
Christof Fetzer , Technische Universitat Dresden
Vincent Gramoli , University of Neuchâtel
Michael Hohmuth , Advancd Micro Devices
Etienne Riviere , University of Neuchatel
Per Stenstrom , Chalmers University of Technology
Osman Unsal , Barcelona Supercomputing Center
Walther Maldonado Moreira , University of Neuchatel
Derin Harmanci , University of Neuchatel
Patrick Marlier , University of Neuchatel
Stephan Diestelhorst , Advanced Micro Devices
Martin Pohlack , Advanced Micro Devices
Adrian Cristal , Barcelona Supercomputing Center
Ibrahim Hur , Barcelona Supercomputing Center
Aleksandar Dragojevic , Ecole Polytechnique Federale de Lausanne
Rachid Guerraoui , Ecole Polytechnique Federale de Lausanne
Michal Kapalka , Ecole Polytechnique Federale de Lausanne
Sasa Tomic , Universitat Politecnica de Catalunya
Guy Korland , Tel Aviv University
Nir Shavit , Tel Aviv University
Martin Nowack , Technische Universitat Dresden
Torvald Riegel , Technische Universitat Dresden
ABSTRACT
The adoption of multi- and many-core architectures for mainstream computing undoubtedly brings profound changes in the way software is developed. In particular, the use of fine grained locking as the multi-core programmer’s coordination methodology is considered by more and more experts as a dead-end. The transactional memory (TM) programming paradigm is a strong contender to become the approach of choice for replacing locks and implementing atomic operations in concurrent programming. Combining sequences of concurrent operations into atomic transactions allows a great reduction in the complexity of both programming and verification, by making parts of the code appear to execute sequentially without the need to program using fine-grained locking. Transactions remove from the programmer the burden of figuring out the interaction among concurrent operations that happen to conflict when accessing the same locations in memory. The EU-funded FP7 VELOX project designs, implements and evaluates an integrated TM stack, spanning from programming language to the hardware support, and including runtime and libraries, compilers, and application environments. This paper presents an overview of the VELOX TM stack and its associated challenges and contributions.
INDEX TERMS
concurrent programming, software transactional memory, hardware transactional memory, compilers, language extensions
CITATION
Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenstrom, Osman Unsal, Walther Maldonado Moreira, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrian Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel, "The Velox Transactional Memory Stack", IEEE Micro, vol.30, no. 5, pp. 76-87, September/October 2010, doi:10.1109/MM.2010.80
REFERENCES
1. M.M. Michael and M.L. Scott, "Simple, Fast, and Practical Non-blocking and Blocking Concurrent Queue Algorithms," Proc. Symp. Principles of Distributed Computing (PODC 96), ACM Press, 1996, pp. 267-275.
2. W. Maldonado et al., "Scheduling Support for Transactional Memory Contention Management," Proc. Symp. Principles and Practices of Parallel Programming (PPoPP 10), ACM Press, 2010, pp. 79-90.
3. D. Christie et al., "Evaluation of AMD's Advanced Synchronization Facility within a Complete Transactional Memory Stack," Proc. European Conf. Computer Systems (Eurosys 10), ACM Press, 2010, pp. 27-40.
4. S. Tomić et al., "EazyHTM: Eager-Lazy Hardware Transactional Memory," Proc. Int'l Symp. Microarchitecture (Micro 09), ACM Press, 2009, pp. 145-155.
5. P. Felber, V. Gramoli, and R. Guerraoui, "Elastic Transactions," Proc. Int'l Symp. Distributed Computing (DISC 09), Springer-Verlag, 2009, pp. 93-107.
6. G. Korland, N. Shavit, and P. Felber, "Noninvasive Concurrency with Java STM," Proc. Programmability Issues for Heterogeneous Multicores (MultiProg 10), 2010; http://www.velox-project.eu/sites/default/ filesmultiprog10.pdf.
7. P. Felber et al., "Time-based Software Transactional Memory," IEEE Trans. Parallel and Distributed Systems, preprint (16 Mar. 2010).
8. D. Dice, O. Shalev, and N. Shavit, "Transactional Locking II," Proc. Int'l Symp. Distributed Computing (DISC 06), Springer-Verlag, 2006, pp. 194-208.
9. F. Zyulkyarov et al., "Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server," Proc. Symp. Principles and Practices of Parallel Programming (PPoPP 09), ACM Press, 2009, pp. 25-34.
10. V. Gajinov et al., "QuakeTM: Parallelizing a Complex Sequential Application Using Transactional Memory," Proc. Int'l Conf. Supercomputing (ICS 09), ACM Press, 2009, pp. 126-135.
11. D. Harmanci et al., "Extensible Transactional Memory Testbed," J. Parallel and Distributed Computing, vol. 70, no. 10, October 2010, pp. 1053-1067.
12. V. Gramoli, D. Harmanci, and P. Felber, "On the Input Acceptance of Transactional Memory." Parallel Processing Letters, vol. 20, no. 1, 2010, pp. 31-50.
13. A. Dragojević et al., "Why STM Can Be More than a Research Toy," Comm. ACM, 2010, to appear.
14. A. Dragojević, R. Guerraoui, and M. Kapalka, "Stretching Transactional Memory," Proc. Conf. Programming Language Design and Implementation (PLDI 09), ACM Press, 2009, pp. 155-165.
15. G. Kestor et al., "RMS-TM: A Transactional Memory Benchmark for Recognition, Mining, and Synthesis Applications," Proc. Workshop Transactional Computing (Transact 09), ACM Press, 2009.
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