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| Theo Ungerer, Francisco Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Casse, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Floria Kluge, Stefan Metzlaff, Jorg Mische, "Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability," IEEE Micro, vol. 30, no. 5, pp. 66-75, September/October, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2010.78, author = {Theo Ungerer and Francisco Cazorla and Pascal Sainrat and Guillem Bernat and Zlatko Petrov and Christine Rochange and Eduardo Quiñones and Mike Gerdes and Marco Paolieri and Julian Wolf and Hugues Casse and Sascha Uhrig and Irakli Guliashvili and Michael Houston and Floria Kluge and Stefan Metzlaff and Jorg Mische}, title = {Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability}, journal ={IEEE Micro}, volume = {30}, number = {5}, issn = {0272-1732}, year = {2010}, pages = {66-75}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2010.78}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability IS - 5 SN - 0272-1732 SP66 EP75 EPD - 66-75 A1 - Theo Ungerer, A1 - Francisco Cazorla, A1 - Pascal Sainrat, A1 - Guillem Bernat, A1 - Zlatko Petrov, A1 - Christine Rochange, A1 - Eduardo Quiñones, A1 - Mike Gerdes, A1 - Marco Paolieri, A1 - Julian Wolf, A1 - Hugues Casse, A1 - Sascha Uhrig, A1 - Irakli Guliashvili, A1 - Michael Houston, A1 - Floria Kluge, A1 - Stefan Metzlaff, A1 - Jorg Mische, PY - 2010 KW - hardware KW - software KW - embedded systems KW - multicore KW - real-time KW - WCET analysis KW - industrial case study VL - 30 JA - IEEE Micro ER - | |||
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1. C. Ballabriga et al., "Otawa: an Open Toolbox for Adaptive WCET Analysis" IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS), Springer, 2010, pp. 35-46.
2. "RapiTime White Paper," Rapita Systems, 2008, http://www.rapitasystems.com/system/files RapiTime-WhitePaper.pdf.
3. A. Bonenfant et al., Coding Guidelines for WCET Analysis Using Measurement-based and Static Analysis Techniques, tech. report IRIT/RR–2010-8–FR, Institut de Recherche en Informatique de Toulouse, Université Paul Sabatier, 2010; ftp://ftp.irit.fr/IRIT/ TRACES/IRIT-RR--2010-8-FR.pdf.
4. J. Mische et al., "How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT," Proc. 23rd Int'l Conf. Architecture of Computing Systems (ARCS 10), Springer-Verlag, 2010, pp. 2-14
5. TriCore 1 User's Manual, v.1.3.8, Infineon Technologies, 2008.
6. J. Mische et al., "Exploiting Spare Resources of In-order SMT Processors Executing Hard Real-time Threads," Proc. IEEE Int'l Conf. Computer Design (ICCD 08), IEEE CS Press, 2008, pp. 371-376.
7. S. Metzlaff et al., "Predictable Dynamic Instruction Scratchpad for Simultaneous Multithreaded Processors," Proc. 9th Workshop Memory Performance (Medea 08), ACM Press, 2008, pp. 38-45.
8. M. Paolieri et al., "Hardware Support for WCET Analysis of Hard Real-Time Multicore Systems," Proc. 36th Int'l Symp. Computer Architecture (ISCA 09), ACM Press, 2009, pp. 57-68.
9. M. Paolieri et al., "An Analyzable Memory Controller for Hard Real-Time CMPs," Embedded Systems Letters, vol. 1, no. 4, Dec. 2009, pp. 86-90.
10. J. Wolf et al., "RTOS Support for Parallel Execution of Hard Real-Time Applications on the Merasa Multicore Processor," Proc. 13th IEEE Int'l Symp. Object/Component/ Service-oriented Real-time Distributed Computing (ISORC 10), IEEE CS Press, 2010, pp. 193-201.
11. M. de Michiel et al., "Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation," Proc. IEEE Int'l Conf. Embedded and Real-Time Computing Systems and Applications (RTCSA 08), IEEE CS Press, 2008, pp. 161-166.
12. C. Rochange and P. Sainrat, "A Context-Parameterized Model for Static Analysis of Execution Times," Trans. High-Performance Embedded Architectures and Compilers (HiPEAC), vol. 2, no. 3, Springer-Verlag, 2007, pp. 109-128.
13. Y.-T.S. Li and S. Malik, "Performance Analysis of Embedded Software using Implicit Path Enumeration," Proc. Workshop Languages, Compilers, and Tools for Real-time Systems, ACM Press, 1995, pp. 88-98.
14. Stratix II DSP Development Board, Reference Manual, Altera Corp., Aug. 2006, http://www.altera.com/literature/manualmnl_stx2_pro_dsp_dev_kit_ep2s180.pdf .
1. J. Kreuzinger et al., "Real-time Scheduling on Multithreaded Processors," Proc. 7th Int'l Conf. Real-Time Computing Systems and Applications, IEEE CS Press, 2000, pp. 155-159.
2. S. Uhrig and J. Wiese, "Jamuth—An IP Processor Core for Embedded Java Real-Time Systems," Proc. 5th Int'l Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 07), ACM Press, 2007, pp. 230-237.
3. M. Schoeberl, "Time-predictable Computer Architecture," EURASIP J. Embedded Systems, vol. 2009, article ID 758480, 2009.
4. A. El-Haj-Mahmoud et al., "Virtual Multiprocessor: An Analyzable, High-Performance Architecture for Real-Time Computing," Proc. Int'l Conf. Compilers, Architectures and Synthesis for Embedded Systems, ACM Press, 2005, pp. 213-224.
5. B. Lickly et al., "Predictable Programming on a Precision Timed Architecture," Proc. Int'l Conf. Compilers, Architectures and Synthesis for Embedded Systems (CASES 08), ACM Press, 2008, pp. 137-146.
6. R. Wilhelm et al., "Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems," IEEE Trans. On CAD of Integrated Circuits and Systems, vol. 28, no. 7, 2009, pp. 966-978.

