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Issue No.05 - September/October (2010 vol.30)
pp: 30-41
Vassilis Papaefstathiou , FORTH-ICS, Heraklion
Stamatis Kavadias , FORTH-ICS, Heraklion
Dionisios Pnevmatikatos , FORTH-ICS, Heraklion
Federico Silla , Universidad Politecnica de Valencia, Valencia
Dimitrios Nikolopoulos , FORTH-ICS, Heraklion
ABSTRACT
<p>A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors' design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency.</p>
INDEX TERMS
interprocessor communication, explicit communication, synchronization, configurable local memory, scratchpad, user-level RDMA, SARC
CITATION
Vassilis Papaefstathiou, Stamatis Kavadias, Dionisios Pnevmatikatos, Federico Silla, Dimitrios Nikolopoulos, "Explicit Communication and Synchronization in SARC", IEEE Micro, vol.30, no. 5, pp. 30-41, September/October 2010, doi:10.1109/MM.2010.77
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