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The SARC Architecture
September/October 2010 (vol. 30 no. 5)
pp. 16-29
Alex Ramirez, Barcelona Supercomputing Center
Felipe Cabarcas, Barcelona Supercomputing Center
Ben Juurlink, Technische Universitat Berlin
Mauricio Alvarez Mesa, Universitat Politecnica de Catalunya
Friman Sanchez, Universitat Politecnica de Catalunya
Arnaldo Azevedo, Delft University of Technology
Cor Meenderinck, Delft University of Technology
Catalin Ciobanu, Delft University of Technology
Sebastian Isaza, Delft University of Technology
Georgi Gaydadjiev, Delft University of Technology

The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.

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Index Terms:
multicore, heterogeneous architecture, accelerator, programming model
Alex Ramirez, Felipe Cabarcas, Ben Juurlink, Mauricio Alvarez Mesa, Friman Sanchez, Arnaldo Azevedo, Cor Meenderinck, Catalin Ciobanu, Sebastian Isaza, Georgi Gaydadjiev, "The SARC Architecture," IEEE Micro, vol. 30, no. 5, pp. 16-29, Sept.-Oct. 2010, doi:10.1109/MM.2010.79
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