Issue No.05 - September/October (2010 vol.30)
Published by the IEEE Computer Society
Mateo Valero , Barcelona Supercomputing Center
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2010.93
<p>In 2004, the European Commission funded the HiPEAC Network of Excellence to improve research in the fields of computer architecture and compilation in Europe. In response to the paradigm shift to multicore-based computers, the European Commission has also invested in several collaborative research projects that investigate a wide range of topics aimed at advancing the state of the art in multicore computing. Most of these projects are defined in the context of the HiPEAC network, and many are in their final phases or successfully completed. This special issue seeks to provide a representative snapshot of the innovations that have taken place in these projects.</p>
As guest editors, we are extremely honored to introduce the IEEE Micro special issue on European multicore computing projects. In 2004, the European Commission funded the HiPEAC Network of Excellence as an instrument to overcome the research landscape fragmentation in the fields of computer architecture and compilation in Europe. In response to the paradigm shift to multicore-based computers, the European Commission has also invested in several collaborative research projects that investigate a wide range of topics aimed at advancing the state of the art in multicore computing, most of which are defined in the context of the HiPEAC network. Many of these projects are in their final phases or successfully completed.
This special issue seeks to provide a rather representative snapshot of the innovations that have taken place in these projects. We anticipated the challenge of addressing projects that had to be performed under collaboration by multiple partners, usually from research institutions and companies located in different European countries and recognized as such by the European Union.
The first article presents ArchExplorer, a Web-based open design exploration framework that overcomes the burdens of parametric exploration using automated architectural composition in order to focus on structural exploration, thus expanding the design space exploration's scope. The authors illustrate their approach through both a careful study of the on-chip memory subsystem and a comprehensive investigation of the impact various multicore system parameters (such as the number of cores and processing elements, cache size, and communication infrastructure bandwidth) have on system power consumption, chip area, and performance. ArchExplorer is one of the great HiPEAC network contributions to our research community.
The next four articles describe some of the main results of the Scalable Computer Architecture project. SARC was one of the three projects supported by the Future and Emerging Technologies initiative in Advanced Computing Architectures launched by the European Commission in 2006. It was concerned with long-term research (year 2015 and onward) in advanced computer architecture, compilation, and programming models. It focused on a systematic, scalable approach to computer systems design, ranging from small energy-critical embedded systems to large-scale networked data servers.
Ramirez et al. describe the SARC heterogeneous architecture and its support for the emerging master-worker programming models. The authors study SARC architecture performance for a set of representative applications from the multimedia, bioinformatics, and scientific domains.
In "Explicit Communication and Synchronization in SARC," Katevenis et al. describe the advanced SARC communication interface, a hardware primitive that unifies the functionalities of a cache controller and network interface. The article describes the synchronization and explicit communication primitives and discusses the SARC robust mechanism for event responses. The authors report full-system simulation results that achieved a 10- to 40-percent speed increase over traditional cache architectures with 64 cores. Other improvements concern on-chip network traffic and lock and barrier latencies.
In their article, Ferrer et al. discuss the scalability and productivity of six parallel programming models for heterogeneous architectures. They conclude that a task-based approach using code and data annotations requires the minimal programming effort while sustaining close to best performance. The proposed programming model motivated the Open MP extension targeting the SARC heterogeneous architecture.
In "SARC Coherence: Scaling Directory Cache Coherence in Performance and Power," Kaxiras and Keramidas describe how to improve the power scalability of shared memory multicores by making directory cache coherence more efficient. The authors show how to eliminate invalidation traffic on writes and directory indirection for finding the writer. The proposed method achieves both significant power and performance improvements compared to a classical MESI protocol.
The last three articles describe projects with focuses ranging from hard real-time embedded multicore design to an automated toolchain for application mapping on heterogeneous platforms.
Ungerer et al. describe the Merasa approach to high-performance, real-time multicore design and analysis techniques that guarantees precise timing analyzability and predictability. The authors validate the proposed hardware and software techniques using a real-world industry-driven scenario.
In "The Velox Transactional-Memory Stack," Felber et al. describe their integrated transactional memory stack, consisting of hardware support, runtime libraries, compilers, programming models, and application environments. The authors carefully evaluate the main challenges of the proposed transactional memory integration into real systems.
Finally, Bertels et al. present the hArtes toolchain for automated application mapping on a heterogeneous platform consisting of an ARM processor, a digital signal processor, and a field-programmable gate array. The authors validate the toolchain using several computationally intensive applications. They show that hArtes supports easy design space exploration while performing application mapping under restricted hardware availability and real-time execution constraints.
We hope that you will enjoy the selected articles, and we encourage you to provide us with your feedback.
Article selection process and reviewers
We received more than 30 contributions from 15 different European projects. The strong sampling of completed and ongoing work in the multicore field was very gratifying. Our first thanks go to all of the authors of the submitted papers, and to all of the reviewers who provided valuable feedback to help improve the papers' content and helped narrow the decision to one appropriate subset. We had to involve David Albonesi, Chuck Moore, and Ronny Ronen to lead the review of papers we had conflicts with. We are honored to have them on board and thank them for their great work.
We assigned a minimum of four reviewers to each paper. The strong quality of the papers made our decision very hard, and finally, due to space constraints, we could select only eight papers for the issue. Because we appreciated the involvement of all of the contributing projects in promoting multicore research in Europe, we convinced the journal to include short summaries of all of the projects with links to their sites (see the "European Multicore Processing Projects" sidebar at the end of this special section). These projects provide a good overview of the variety of topics the European research community is addressing. Please do not hesitate to contact the project coordinators if you need more information on a specific topic.
We thank Panos Tsarchopoulos, our project officer at the European Commission, for his unconditional support for multicore computing research. He strongly believes in the strengths and the high quality of the European research community, and continues to successfully support our research field inside the European Commission, as is indicated by the continuously increasing funding for this important topic. We would like to especially acknowledge Stamatis Vassiliadis, a great scientist and human being who was one of the main driving forces behind the establishment of the HiPEAC, SARC, and hArtes projects presented in this special issue. Unfortunately, we lost Stamatis in April 2007, and so our HiPEAC research community and the SARC and hArtes projects were unable to benefit from his deep technical insight, enormous enthusiasm, and borderless drive. We are grateful to David Albonesi, IEEE Micro's editor in chief, for his continuous support throughout the process. We thank again all those who contributed time and effort to selecting the articles and making suggestions for improvements. Finally, thanks to Debby Mosher, administrator for IEEE Micro, for managing the submission and evaluation process, and Joan Taylor for overseeing and building the final version of the issue.
Mateo Valero is a professor in the Computer Architecture Department at the Universitat Politècnica de Catalunya (UPC) and the director of the Barcelona Supercomputing Center, the National Center of Supercomputing in Spain. His research interests focuses on high-performance architectures. Valero has a PhD in telecommunications from UPC. He is a Fellow of IEEE and the ACM and an Intel Distinguished Research Fellow.
Nacho Navarro is an associate professor of computer engineering at the Universitat Politècnica de Catalunya (UPC) and a senior researcher at the Barcelona Supercomputing Center. His research interests include heterogeneous accelerators (FPGAs and GPUs), runtime support for parallelism and operating systems for multicores Navarro has a PhD in computer science from UPC. He a member of IEEE, the IEEE Computer Society, and the ACM.