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Fine-Grained Activation for Power Reduction in DRAM
May/June 2010 (vol. 30 no. 3)
pp. 34-47
Elliott Cooper-Balis, University Of Maryland,
Bruce Jacob, U. of Maryland,

This DRAM architecture optimization, which appears transparent to the memory controller, significantly reduces power consumption. With trivial additional logic, using the posted-CAS command enables a finer-grained selection when activating a portion of the DRAM array. Experiments show that, in a high-use memory system, this approach can reduce total DRAM device power consumption by up to 40 percent.

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Index Terms:
DRAM, memory system, low-power design, posted-CAS command, fine-grained activation, DRAMsim
Citation:
Elliott Cooper-Balis, Bruce Jacob, "Fine-Grained Activation for Power Reduction in DRAM," IEEE Micro, vol. 30, no. 3, pp. 34-47, May-June 2010, doi:10.1109/MM.2010.43
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