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Issue No.02 - March/April (2010 vol.30)
pp: 70-79
Tony M. Brewer , Convey Computer
ABSTRACT
<p>The Convey HC-1 is a heterogeneous computing system based on an industry-standard Intel processor and a proprietary coprocessor that share virtual memory and an instruction stream, creating a hybrid-core computing system. The coprocessor architecture supports user-defined, dynamically loadable instruction sets. Managing the decoding, dispatch, and execution of completely user-defined instructions requires an innovative approach to system design and operation.</p>
INDEX TERMS
heterogeneous computing, hybrid-core computing, instruction set design, FPGAs, reconfigurable computing, coprocessors, accelerators
CITATION
Tony M. Brewer, "Instruction Set Innovations for the Convey HC-1 Computer", IEEE Micro, vol.30, no. 2, pp. 70-79, March/April 2010, doi:10.1109/MM.2010.36
REFERENCES
1. A. Shan, "Heterogeneous Processing: A Strategy for Augmenting Moore's Law," Linux J.,2 Jan. 2006, www.linuxjournal.com/article8368.
2. D. Thomas and P. Moorby, The Verilog Hardware Description Language, Springer, 2008.
3. InsPecT: A Proteomics Search Toolkit, tech. report, Univ. of California, San Diego, Computer Science and Eng. Dept., 2007, http://proteomics.ucsd.edu/InspectDocsindex.html .
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