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Issue No.02 - March/April (2010 vol.30)
pp: 16-29
Nathan Kalyanasundharam , Advanced Micro Devices
Gregg Donley , Advanced Micro Devices
Kevin Lepak , Advanced Micro Devices
Bill Hughes , Advanced Micro Devices
ABSTRACT
<p>The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature, the probe filter, reduces both the bandwidth overhead of traditional broadcast-based coherence and memory latency.</p>
INDEX TERMS
processor, x86-64, multiprocessor, memory hierarchy, cache, cache directory, probe filter, system interconnect, HyperTransport3 technology, blade server, power envelopes
CITATION
Nathan Kalyanasundharam, Gregg Donley, Kevin Lepak, Bill Hughes, "Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor", IEEE Micro, vol.30, no. 2, pp. 16-29, March/April 2010, doi:10.1109/MM.2010.31
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