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Issue No.02 - March/April (2010 vol.30)
pp: 7-15
Ron Kalla , IBM
ABSTRACT
<p>The Power7 is IBM's first eight-core processor, with each core capable of four-way simultaneous-multithreading operation. Its key architectural features include an advanced memory hierarchy with three levels of on-chip cache; embedded-DRAM devices used in the highest level of the cache; and a new memory interface. This balanced multicore design scales from 1 to 32 sockets in commercial and scientific environments.</p>
INDEX TERMS
processor, IBM, Power7, eDRAM, DDR3, RAS, SMT operation, PowerPC architecture
CITATION
Ron Kalla, Balaram Sinharoy, William J. Starke, Michael Floyd, "Power7: IBM's Next-Generation Server Processor", IEEE Micro, vol.30, no. 2, pp. 7-15, March/April 2010, doi:10.1109/MM.2010.38
REFERENCES
1. R. Kalla and B. Sinharoy, "Power7: IBM's Next Generation Power Microprocessor," IEEE Symp. High-Performance Chips (Hot Chips 21), 2009.
2. J.M. Tender et al., "Power4 System Micro Architecture," IBM J. Research and Development, vol. 46, no. 1, 2002, pp. 5-25.
3. B. Sinharoy et al., "Power5 System Micro Architecture," IBM J. Research and Development, vol. 49, no. 4/5, 2005, pp. 505-521.
4. J. Barth et al., "A 500 MHz Random Cycle, 1.5ns-Latency, SOI eDRAM Macro Featuring a 3T Micro Sense Amplifier," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 486-487.
5. H.Q. Le et al., "IBM Power6 Micro Architecture," IBM J. Research and Development, vol. 51, no. 6, 2007, pp. 639-662.
6. W. Starke, "Power7: IBM's Next Generation, Balanced Power Server Chip," IEEE Symp. High-Performance Chips (Hot Chips 21), 2009.
7. Power ISA Version 2.06," IBM, Jan. 2009; http://www.power.org/resources/downloads PowerISA_V2.06_PUBLIC.pdf.
8. R. Kalla, B. Sinharoy, and J.M. Tendler, "IBM Power5 Chip: A Dual-Core Multithreaded Processor," IEEE Micro, vol. 24, no. 2, 2004, pp. 40-47.
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