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Accelerating Critical Section Execution with Asymmetric Multicore Architectures
January/February 2010 (vol. 30 no. 1)
pp. 60-70
M. Aater Suleman, University of Texas at Austin
Onur Mutlu, Carnegie Mellon University
Moinuddin K. Qureshi, IBM Research
Yale N. Patt, University of Texas at Austin

Contention for critical sections can reduce performance and scalability by causing thread serialization. The proposed accelerated critical sections mechanism reduces this limitation. ACS executes critical sections on the high-performance core of an asymmetric chip multiprocessor (ACMP), which can execute them faster than the smaller cores can.

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Index Terms:
multicore, CMP, critical sections, heterogeneous cores, parallel programming, locks, serialization
Citation:
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt, "Accelerating Critical Section Execution with Asymmetric Multicore Architectures," IEEE Micro, vol. 30, no. 1, pp. 60-70, Jan.-Feb. 2010, doi:10.1109/MM.2010.7
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