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Making Address-Correlated Prefetching Practical
January/February 2010 (vol. 30 no. 1)
pp. 50-59
Thomas F. Wenisch, University of Michigan
Michael Ferdman, Carnegie Mellon University
Anastasia Ailamaki, École Polytechnique Fédérale de Lausanne
Babak Falsafi, École Polytechnique Fédérale de Lausanne
Andreas Moshovos, University of Toronto

Despite a decade of research demonstrating its efficacy, address-correlated prefetching has never been implemented in a shipping processor because it requires megabytes of metadata—too large to store practically on chip. New storage-, latency-, and bandwidth-efficient mechanisms for storing metadata off chip yield a practical design that achieves 90 percent of the performance potential of idealized on-chip metadata storage.

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Index Terms:
cache memories, address-correlated prefetching
Citation:
Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos, "Making Address-Correlated Prefetching Practical," IEEE Micro, vol. 30, no. 1, pp. 50-59, Jan.-Feb. 2010, doi:10.1109/MM.2010.21
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