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Architecture Design of Versatile Recognition Processor for Sensornet Applications
November/December 2009 (vol. 29 no. 6)
pp. 44-57
Yuichi Hori, Keio University
Yuya Hanai, Keio University
Jun Nishimura, Keio University
Tadahiro Kuroda, Keio University

This article presents the multiobject parallel recognition architecture of a versatile recognition processor (VRP) that detects and recognizes objects from images, videos, sounds, and acceleration signals. It offers eight times better power efficiency than conventional object recognition processors, making it ideal for mobile application platforms and wireless sensor network systems.

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Index Terms:
recognition, wireless sensor network, Haar-like feature, AdaBoost, real time, low power
Citation:
Yuichi Hori, Yuya Hanai, Jun Nishimura, Tadahiro Kuroda, "Architecture Design of Versatile Recognition Processor for Sensornet Applications," IEEE Micro, vol. 29, no. 6, pp. 44-57, Nov.-Dec. 2009, doi:10.1109/MM.2009.93
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