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Issue No.05 - September/October (2009 vol.29)
pp: 46-55
Hsiang-Ning Liu , National Central University, Taiwan
Yu-Jen Huang , National Central University, Taiwan
Jin-Fu Li , National Central University, Taiwan
ABSTRACT
<p>Using a packet-based built-in self test for RAM cores in mesh-based networks on chip (NoC) can reduce the BIST circuit's area cost. The proposed scheme reuses the NoC to transport test patterns to RAM such that routing doesn't limit the number of RAM cores tested. The scheme also achieves higher test parallelism than a typical parallel BIST by interleaving the read/write test operations.</p>
INDEX TERMS
network-on-chip, multicore, random access memory, march test, BIST, testing.
CITATION
Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li, "Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks", IEEE Micro, vol.29, no. 5, pp. 46-55, September/October 2009, doi:10.1109/MM.2009.83
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