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Dynamic Multicore Resource Management: A Machine Learning Approach
September/October 2009 (vol. 29 no. 5)
pp. 8-17
José F. Martínez, Cornell University
Engin İpek, University of Rochester

A machine learning approach to multicore resource management produces self-optimizing on-chip hardware agents capable of learning, planning, and continuously adapting to changing workload demands. This results in more efficient and flexible management of critical hardware resources at runtime.

1. S. Rixner et al., "Memory Access Scheduling," Proc. Int'l Symp. Computer Architecture (ISCA 00), IEEE CS Press, 2000, pp. 128-138.
2. T. Dunigan et al., "Early Evaluation of the Cray X1," Proc. Supercomputing (SC 03), IEEE CS Press, 2003, p. 18.
3. P. Kongetira et al., "Niagara: A 32-Way Multithreaded SPARC Processor," IEEE Micro, vol. 25, no. 2, 2005, pp. 21-29.
4. J.D. McCalpin, "Sustainable Memory Bandwidth in Current High Performance Computers," http://www.cs.virginia.edu/~mccalpin/papers/ bandwidthbandwidth.html.
5. M. Joshi et al., "ScalParC: A New Scalable and Efficient Parallel Classification Algorithm for Mining Large Datasets," Proc. Int'l Parallel Processing Symp. (IPPS 98), IEEE CS Press, 1998, pp. 573.
6. E. İpek et al., "Self-Optimizing Memory Controllers: A Reinforcement Learning Approach," Proc. Int'l Symp. Computer Architecture (ISCA 08), IEEE CS Press, 2008, pp. 39-50.
7. D. Bertsekas, Neuro Dynamic Programming, Athena Scientific, 1996.
8. R. Sutton and A. Barto, Reinforcement Learning, MIT Press, 1998.
9. S. Rixner, "Memory Controller Optimizations for Web Servers," Proc. Int'l Symp. Microarchitecture (MICRO 04), IEEE CS Press, 2004, pp. 355-366.
10. C. Isci et al., "An Analysis of Efficient Multi-core Global Power Management Policies: Maximizing Performance for a Given Power Budget," Proc. Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 347-358.
11. M. Qureshi and Y. Patt, "Utility-based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches," Proc. Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 423-432.
12. R. Bitirgen, E. İpek, and J.F. Martínez, "Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach," Proc. Int'l Symp. Microarchitecture (MICRO 08), IEEE CS Press, 2008, pp. 318-329.
13. J.L. Henning, "SPEC CPU2000: Measuring CPU Performance in the New Millennium," Computer, vol. 33, no. 7, 2000, pp. 28-35.
14. D.H. Bailey et al., NAS Parallel Benchmarks, tech. report RNR-94-007, NASA Ames Research Center, 1994.
15. S. Choi and D. Yeung, "Learning-based SMT Processor Resource Distribution via Hill-Climbing," Proc. Int'l Symp. Computer Architecture (ISCA 06), IEEE CS Press, 2006, pp. 239-251.
16. K.J. Nesbit et al. , "Fair Queueing memory Systems," Proc. Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 208-222.

Index Terms:
multicore, dynamic resource management, machine learning.
Citation:
José F. Martínez, Engin İpek, "Dynamic Multicore Resource Management: A Machine Learning Approach," IEEE Micro, vol. 29, no. 5, pp. 8-17, Sept.-Oct. 2009, doi:10.1109/MM.2009.77
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