Issue No.05 - September/October (2009 vol.29)
Published by the IEEE Computer Society
David H. Albonesi , firstname.lastname@example.org
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2009.78
<p>IEEE Micro Editor in Chief David H. Albonesi welcomes six new emmbers to teh IEEE Micro Editorial Board and previews this general interest issue.</p>
With this issue, I have the honor of welcoming six new members to the IEEE Micro Editorial Board: Alper Buyuktosunoglu, Kris Flautner, Steve Keckler, Norm Jouppi, Margaret Martonosi, and Shubu Mukherjee. Rather than write something about each of them, I'll let the biographies of this distinguished group of industry and academic leaders speak for themselves (see the sidebar). I am truly humbled that they accepted my invitation to join the Board.
Coming up in our last issue of 2009 is a new column. This column will feature brief tutorials, but not in the traditional sense of "this is how this thing works." Rather, the column is part tutorial, part opinion piece. I invite you to check it out. Coming in 2010 is a second new column and, after Top Picks and Hot Chips, issues on computer architecture debates and datacenter computing.
Here's a brief introduction to the five articles in this general interest issue. They cover a wide range of subjects of interest to the Micro community: multicore computer architecture, benchmark analysis, real-time operating systems (RTOSs), test, and security.
Our cover feature article, "Dynamic Multicore Resource Management: A Machine Learning Approach," by José Martínez and Engin İpek, introduces a novel machine learning strategy to effectively manage shared resources in multicore microprocessors. The authors advocate a departure from conventional heuristic-based policies in favor of a new direction in which the architect specifies the objective function and determines the most appropriate machine learning approach and the variables to be considered. The authors demonstrate through two case studies that the resulting self-optimizing system achieves far better performance than current state-of-the-art control policies.
In the second article, "A Benchmark Characterization of the EEMBC Benchmark Suite," Jason Poovey, Thomas Conte, Markus Levy, and Shay Gal-On present a detailed evaluation of EEMBC, a popular benchmark suite for embedded microprocessors. Vendors often rely on standard benchmark results to assess the most suitable microprocessor for their particular applications. However, it's difficult in practice to know which standard benchmarks are most representative. The authors present a methodology for benchmark characterization that exposes a program's key attributes, and they demonstrate their approach using the EEMBC suite.
Tran Nguyen Bao Anh and Su-Lim Tan provide an in-depth analysis of RTOSs for embedded processor systems in their article, "Real-Time Operating Systems for Small Microcontrollers." The authors provide a broad comparison of 14 RTOSs using criteria such as scheduling approach, system call/API support, and documentation. From this list, they identify four RTOSs with particularly rich system API support, and quantitatively compare them on an embedded platform, using oscilloscopes and logic analyzers to make accurate timing measurements.
Next, in "Memory Built-In Self Test in Multicore Chips with Mesh-Based Networks," Hsiang-Ning Liu, Yu-Jen Huang, and Jin-Fu Li propose a memory built-in self test (BIST) approach suitable for multicore chips with packet-based networks. Because multicore chips have identical memories situated throughout the die, a single BIST circuit can broadcast test packets through the network to multiple memories, thereby achieving parallel test with lower overhead than dedicated BIST circuits. The authors describe the required network-on-chip support for their parallel BIST technique, and show that their implementation achieves modest overhead with fast test speeds.
The last article, "Hardware-Software Codesign for High-Speed Signature-Based Virus Scanning," by Ying-Dar Lin, Po-Ching Lin, Yuan-Cheng Lai, and Tai-Ying Liu, describes their BFAST* scanning engine and its integration with Clam AntiVirus. The BFAST architecture searches in sublinear time by querying Bloom filters to derive the shift distance in the search window. The article describes the modules that BFAST* offloads from ClamAV and the communication interface. By implementing their system on a field-programmable gate array platform, the authors identify the performance bottlenecks and propose remedies for future work.
I hope you enjoy these articles, and I always welcome your feedback at email@example.com.
Editor in Chief