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Coherency Hub Design for Multisocket Sun Servers with CoolThreads Technology
July/August 2009 (vol. 29 no. 4)
pp. 36-47
John Feehrer, Sun Microsystems
Paul Rotker, Sun Microsystems
Milton Shih, Sun Microsystems
Paul Gingras, Sun Microsystems
Peter Yakutis, Sun Microsystems
Stephen Phillips, Sun Microsystems
John Heath, University of Southern Maine

CoHub, a coherency hub ASIC, provides a cost-effective way to extend a glueless two-node chip-multithreading system to a four-node system without changes to the processor. The four-node, 256-thread system achieves near-linear scaling of performance with thread count on transaction-processing workloads. Time-to-market pressure, 800-MHz operation, and a six-stage pipeline were among the constraints that shaped CoHub's design.

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2. J. Feehrer et al., "Coherency Hub Design for Multi-Node Victoria Falls Systems," Hot Interconnects 16, 2008; http://www.hoti.org/archive/2008papers2008_S2_1.pdf .
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4. "UltraSPARC IV Processor Architecture Overview," white paper, Sun Microsystems, Feb. 2004; http://www.sun.com/processors/whitepapers us4_whitepaper.pdf.
5. "Low Pin Count Interface Specification," Intel, Aug. 2002; http://www.intel.com/design/chipsets/industry 25128901.pdf.
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Index Terms:
chip multithreading, UltraSparc, cache coherency, multiprocessor interconnect, SpecCPU2006, SPEC, AppServer2004, hardware
Citation:
John Feehrer, Paul Rotker, Milton Shih, Paul Gingras, Peter Yakutis, Stephen Phillips, John Heath, "Coherency Hub Design for Multisocket Sun Servers with CoolThreads Technology," IEEE Micro, vol. 29, no. 4, pp. 36-47, July-Aug. 2009, doi:10.1109/MM.2009.62
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