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Practical High-Throughput Crossbar Scheduling
July/August 2009 (vol. 29 no. 4)
pp. 22-35
Nikos Chrysos, Foundation for Research and Technology—Hellas
Giorgos Dimitrakopoulos, Foundation for Research and Technology—Hellas

A practical deterministic crossbar scheduler achieves almost full throughput without being heavily affected by short virtual output queues or traffic burstiness. Simple additions offer deterministic service guarantees and distribute the bandwidth of congested links in a weighted, fair manner.

1. P. Gupta and N. McKeown, "Design and Implementation of a Fast Crossbar Scheduler," IEEE Micro, vol. 19, no. 1, Jan./Feb. 1999, pp. 20-28.
2. L. Tassiulas, "Linear Complexity Algorithms for Maximum Throughput in Radio Networks and Input Queues Switches," Proc. IEEE Infocom, IEEE Press, 1998, pp. 533-539.
3. P. Giaccone, B. Prabhakar, and D. Shah, "Randomized Scheduling Algorithms for High-Aggregate Bandwidth Switches," IEEE J. Selected Areas Comm., vol. 21, no. 4, May 2003, pp. 546-559.
4. I. Keslassy and N. McKeown, "Analysis of Scheduling Algorithms that Provide 100% Throughput in Input-Queued Switches," Proc. 39th Allerton Conf. Comm., Control, and Computing, 2001; http://tiny-tera.stanford. edu/~nickm/papers allerton2001.pdf.
5. D. Serpanos and P. Antoniadis, "FIRM: A Class of Distributed Scheduling Algorithms for High-Speed ATM Switches with Multiple Input Queues," Proc. IEEE Infocom, IEEE Press, 2000, pp. 548-555.
6. Y. Li, S. Panwar, and H.J. Chao, "Exhaustive Service Matching Algorithms for Input Queued Switches," Proc. IEEE High Performance Switching and Routing (HPSR), IEEE Press, 2004, pp. 253-258.
7. J. Liu et al., "Stable Round-Robin Scheduling Algorithms for High-Performance Input-Queued Switches," Proc. IEEE Hot Interconnects, IEEE CS Press, 2002, p. 43.
8. N. Chrysos and M. Katevenis, "Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics," Proc. IEEE Infocom, IEEE Press, 2006, pp. 1-13.
9. N. Kumar, N.R. Pan, and D. Shah, "Fair Scheduling in Input-Queued Switches under Inadmissible Traffic," Proc. IEEE Globecom, IEEE Press, 2004, pp. 1713-1717.
10. L. Kalampoukas et al., "High-Speed Parallel-Prefix Modulo 2n−1 Adders," IEEE Trans. Computers, vol. 49, no. 7, July 2000, pp. 673-680.

Index Terms:
interconnections, packet switching, crossbar scheduler, VLSI design, hardware
Citation:
Nikos Chrysos, Giorgos Dimitrakopoulos, "Practical High-Throughput Crossbar Scheduling," IEEE Micro, vol. 29, no. 4, pp. 22-35, July-Aug. 2009, doi:10.1109/MM.2009.71
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