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Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
May/June 2009 (vol. 29 no. 3)
pp. 20-30
ASCII Text
x 
 
Jiang Xu, Wayne Wolf, Wei Zhang, "Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs," IEEE Micro, vol. 29, no. 3, pp. 20-30, May/June, 2009.
 
 
BibTex
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@article{ 10.1109/MM.2009.40,
author = {Jiang Xu and Wayne Wolf and Wei Zhang},
title = {Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs},
journal ={IEEE Micro},
volume = {29},
number = {3},
issn = {0272-1732},
year = {2009},
pages = {20-30},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2009.40},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
IS - 3
SN - 0272-1732
SP20
EP30
EPD - 20-30
A1 - Jiang Xu,
A1 - Wayne Wolf,
A1 - Wei Zhang,
PY - 2009
KW - network on chip
KW - multiprocessor
KW - system on chip
KW - asynchronous
KW - wave pipeline
KW - low power
KW - double data rate
KW - interconnect
VL - 29
JA - IEEE Micro
ER -
 
Jiang Xu, Hong Kong University of Science and Technology
Wayne Wolf, Georgia Institute of Technology
Wei Zhang, Princeton University

DWP, a new interconnect structure for asynchronous networks on chip in multiprocessing SoCs, yields higher throughput, consumes less power, suffers less from crosstalk noise, and requires less area than traditional interconnect structures. Its advantages stem from techniques including wave pipelining, double-data-rate transmission, interleaved lines, misaligned repeaters, and clock gating.

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Index Terms:
network on chip, multiprocessor, system on chip, asynchronous, wave pipeline, low power, double data rate, interconnect
Citation:
Jiang Xu, Wayne Wolf, Wei Zhang, "Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs," IEEE Micro, vol. 29, no. 3, pp. 20-30, May-June 2009, doi:10.1109/MM.2009.40
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