The Community for Technology Leaders
RSS Icon
Issue No.03 - May/June (2009 vol.29)
pp: 10-19
Thomas B. Berg , MIPS Technologies
<p>In embedded systems, multiple cores mean multiple caches and often multiple cache levels. Consequently, maintaining coherency between the cores' caches and the data generated or consumed by I/O devices is challenging, with different solutions trading off hardware versus software complexity. The optimal approach for I/O data coherence depends on application and system characteristics, and might require a combination of techniques.</p>
multicore, I/O coherence, hardware/software interfaces, memory hierarchy, embedded systems, coherence manager, cache
Thomas B. Berg, "Maintaining I/O Data Coherence in Embedded Multicore Systems", IEEE Micro, vol.29, no. 3, pp. 10-19, May/June 2009, doi:10.1109/MM.2009.44
1. G.T. Byrd and M.J. Flynn, "Producer-Consumer Communication in Distributed Shared Memory Multiprocessors," Proc. IEEE, vol. 87, no. 3, Mar 1999, pp. 456-466.
2. J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, 2002.
3. M. Dubois, C. Scheurich, and F.A. Briggs, "Synchronization, Coherence, and Event Ordering in Multiprocessors," Computer, vol. 21, no. 2, Feb. 1988, pp. 9-21.
4. PCI Local Bus Specification Rev. 2.2, PCI Special Interest Group, Dec. 1998.
5. M. Knoth, "Achieving Cache Coherence in a MIPS32 Multicore Design," Aug. 2008; 209600568.
6. M. Throndson, "Single-Chip Coherent Multiprocessing Is Next Step," EETimes,20 May 2008; .
7. D. Abramson et al., "Intel Virtualization Technology for Directed I/O," Intel Technology J., vol. 10, no. 3, 10 Aug. 2006.
8. M. Ben-Yehuda et al. "The Price of Safety: Evaluating IOMMU Performance," Proc. 2007 Ottawa Linux Symp., 2007; Reprint.pdf .
35 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool