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Godson-3: A Scalable Multicore RISC Processor with x86 Emulation
March/April 2009 (vol. 29 no. 2)
pp. 17-29
Weiwu Hu, Institute of Computing Technology, Chinese Academy of Sciences
Jian Wang, Institute of Computing Technology, Chinese Academy of Sciences
Xiang Gao, Institute of Computing Technology, Chinese Academy of Sciences
Yunji Chen, Institute of Computing Technology, Chinese Academy of Sciences
Qi Liu, Institute of Computing Technology, Chinese Academy of Sciences
Guojie Li, Institute of Computing Technology, Chinese Academy of Sciences

The Godson-3 microprocessor aims at high-throughput server applications, high-performance scientific computing, and high-end embedded applications. It offers a scalable network on chip, hardware support for x86 emulation, and a reconfigurable architecture. The four-core Godson-3 chip is fabricated with 65-nm CMOS technology. Eight- and 16-core Godson-3 chips are in development.

1. R. Kessler, "The Alpha 21264 Microprocessor," IEEE Micro, vol. 19, no. 2, Mar./Apr. 1999, pp. 24-36.
2. K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor," IEEE Micro, vol. 16, no. 2, Mar./Apr. 1996, pp. 28-41.
3. T. Horel and G. Lauterbach, "UntraSparc-III: Designing Third-Generation 64-bit Performance," IEEE Micro, vol. 19, no. 3, May/June 1999, pp. 73-85.
4. A. Kumar, "The HP PA-8000 RISC CPU," IEEE Micro, vol. 17, no. 2, Mar./Apr. 1997, pp. 27-32.
5. R. Kalla et al., "IBM POWER5 Chip: A Dual-Core Multithreaded Processor," IEEE Micro, vol. 24, no. 2, Mar./Apr. 2004, pp. 40-47.
6. P. Kongetira et al., "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, Mar./Apr. 2005, pp. 21-29.
7. K. Sankaralingam et al., "Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture," Proc. 30th Int'l Symp. Computer Architecture (ISCA 03), ACM Press, 2003, pp. 422-433.
8. W. Hu et al., "Microarchitecture of the Godson-2 Processor," J. Computer Science and Technology, vol. 20, no. 2, Mar. 2005, pp. 243-249.
9. A. Klaiber, "The Technology behind Crusoe Processors," white paper, Transmeta Corp., Jan. 2000.
10. A. Chernoff et al., "FX!32: A Profile-Directed Binary Translator," IEEE Micro, vol. 18, no. 2, Mar./Apr. 1998, pp. 56-64.
11. K. Ebcioglu et al., "Dynamic Binary Translation and Optimization," IEEE Trans. Computers, vol. 50, no. 6, June 2001, pp. 529-548.
12. F. Bellard, "QEMU, a Fast and Portable Dynamic Translator," Proc. Usenix Ann. Technical Conf., Usenix Assoc., 2005, pp. 41-46.
13. Incisive Xtreme Series Datasheet, http://www.cadence.com/rl/Resources/datasheets Cadence_6569_DS_R2.pdf.

Index Terms:
multicore processor, RISC processor, scalable interconnection network, reconfigurable architecture, x86 emulation
Citation:
Weiwu Hu, Jian Wang, Xiang Gao, Yunji Chen, Qi Liu, Guojie Li, "Godson-3: A Scalable Multicore RISC Processor with x86 Emulation," IEEE Micro, vol. 29, no. 2, pp. 17-29, March-April 2009, doi:10.1109/MM.2009.30
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