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Rock: A High-Performance Sparc CMT Processor
March/April 2009 (vol. 29 no. 2)
pp. 6-16
Shailender Chaudhry, Sun Microsystems
Robert Cypher, Sun Microsystems
Magnus Ekman, Sun Microsystems
Martin Karlsson, Sun Microsystems
Anders Landin, Sun Microsystems
Sherman Yip, Sun Microsystems
Håkan Zeffer, Sun Microsystems
Marc Tremblay, Sun Microsystems

Rock, Sun's third-generation chip-multithreading processor, contains 16 high-performance cores, each of which can support two software threads. Rock uses a novel checkpoint-based architecture to support automatic hardware scouting under a load miss, speculative out-of-order retirement of instructions, and aggressive dynamic hardware parallelization of a sequential instruction stream. It is also the first processor to support transactional memory in hardware.

1. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, no. 2, 2005, pp. 21-29.
2. G.M. Amdahl, "Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities," Proc. AFIPS Conf., vol. 30, AFIPS Press, 1967, pp. 483-485.
3. M.D. Hill and M.R. Marty, "Amdahl's Law in the Multicore Era," Computer, vol. 41, no. 7, 2008, pp. 33-38.
4. M. Tremblay and S. Chaudhry, "A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread SPARC Processor," Proc. Int'l Solid-State Circuits Conf. Digest of Technical Papers (ISSCC 08), IEEE Press, 2008, pp. 82-83.
5. M. Herlihy and J.E.B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures," Proc. IEEE/ACM Int'l Symp. Computer Architecture (ISCA 93), ACM Press, 1993, pp. 289-300.
6. M. Tremblay, B. Joy, and K. Shin, "A Three Dimensional Register File for Superscalar Processors," Proc. Hawaii Int'l Conf. System Sciences (HICSS 95), IEEE CS Press, 1995, pp. 191-201.
7. SPARC Int'l, The SPARC Architecture Manual (version 9), Prentice-Hall, 1994.
8. H. Akkary, R. Rajwar, and S.T. Srinivasan, "Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors," Proc. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 03), IEEE CS Press, 2003, pp. 423-434.
9. W.W. Hwu and Y.N. Patt, "Checkpoint Repair for Out-of-Order Execution Machines," Proc. IEEE/ACM Int'l Symp. Computer Architecture (ISCA 87), ACM Press, 1987, pp. 18-26.
10. S.T. Srinivasan et al., "Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance," IEEE Micro, vol. 24, no. 6, 2004, pp. 62-73.
11. A. Cristal et al., "Out-of-Order Commit Processors," Proc. IEEE Int'l Symp. High-Performance Computer Architectures (HPCA 04), IEEE CS Press, 2004, pp. 48-59.
12. J. Dundas and T. Mudge, "Improving Data Cache Performance by Pre-Executing Instructions Under a Cache Miss," Proc. Int'l Conf. Supercomputing (ICS 97), ACM Press, 1997, pp. 68-75.
13. O. Mutlu et al., "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors," Proc. IEEE Int'l Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 129-140.
14. S. Chaudhry et al., "High-Performance Throughput Computing," IEEE Micro, vol. 25, no. 3, 2005, pp. 32-45.

Index Terms:
system architectures, integration and modeling, processor architectures, multithreaded processors, multicore/single-chip multiprocessors, parallel architectures, speculative multithreading
Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay, "Rock: A High-Performance Sparc CMT Processor," IEEE Micro, vol. 29, no. 2, pp. 6-16, March-April 2009, doi:10.1109/MM.2009.34
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