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Issue No.02 - March/April (2009 vol.29)
pp: 4-5
Published by the IEEE Computer Society
Christos Kozyrakis , Stanford University
Jan-Willem van de Waerdt , NXP Semiconductors
ABSTRACT
In this special issue, IEEE Micro presents a selection of articles from the best presentations from the Hot Chips 2008 conference.




In August 2008, the annual Hot Chips conference celebrated its 20th anniversary. As the guest editors for this special issue of IEEE Micro, we are pleased to introduce a selection of articles based on the best presentations from the conference program.
Hot Chips is a unique conference in all aspects. In contrast to other events that tend to focus on academic research or marketing issues, Hot Chips focuses on technical innovations in the latest chip designs and related technologies. Companies present the chips for upcoming or recent products and discuss technical insights not easily found elsewhere. To complement the program, a select set of research groups presents prototype devices that showcase ideas ready for industrial adoption.
The conference focuses on quality rather than quantity. The single track of presentations routinely draws an audience of 600 industry practitioners and researchers. To attract submissions from overloaded and deadline-driven engineers, the conference acceptance is based on a short abstract and the conference proceedings include only the final presentation, rather than a set of long papers. All members of the program committee reviewed each of the 64 submissions for Hot Chips 20 and selected the best 25 based on technical merit and innovation.
The 2008 program reflects three important trends in the semiconductor industry. The most pervasive trend is the widespread adoption of multicore designs across all industry domains. Designs with hundreds of cores, transactional memory, and support for massive data-level parallelism are some of this year's highlights. The second trend is the emergence of domain or application-specific designs that provide large improvements in terms of performance per watt over general-purpose chips for handheld and supercomputing systems. The final trend is toward complexity-effective design techniques using new generations of configurable devices or customizable platforms for multicore architectures.
For this special issue of IEEE Micro, we selected five presentations that capture these three trends and asked the authors to extend them into full articles.
Complexity-effective multicore chip
In "Rock: A High-Performance SPARC CMT Processor," Shailender Chaudhry and his colleagues describe Sun Microsystems' latest chip multithreading (CMT) chip. The Rock architecture uses a single mechanism for speculative thread execution to improve instruction-level parallelism, tolerate memory latency, and simplify parallel programming through transactional memory. The unified mechanism allows for a multicore design that reduces complexity, area, and power requirements.
RISC multicore for x86 emulation
In "Godson-3: A Scalable Multicore RISC Processor with x86 Emulation," Weiwu Hu and his colleagues present the third-generation Godson design developed at the Chinese Academy of Sciences. The scalable chip is based on an out-of-order, reduced-instruction-set computer (RISC) core and a mesh interconnect scheme. To ease adoption in desktop and notebook systems, it also implements a set of instruction-set extensions that accelerate the execution of x86 binary code on the RISC cores using dynamic binary translation.
Architecture platform for DSP processing
The video processing domain demands high performance and flexibility to address a wide range of applications and systems. In "Broadcom mediaDSP: A Platform for Building Programmable Multicore Video Processors," Rich Selvaggi and Larry Pearlstein describe the components and philosophy for a modular and scalable platform for multicore chips in this domain. Broadcom has applied its platform approach to realize a single-chip, high-definition frame rate converter for 120-Hz LCD television sets.
Bridging FPGA and ASIC development
The increased logic and memory capacity and the flexibility of interconnect have made field-programmable gate array (FPGA) technology an increasingly attractive alternative to full-custom chip designs for applications ranging from digital signal processing and networking tasks to supercomputing acceleration. This trend is reinforced by increased mask costs associated with the latest complementary metal-oxide semiconductor (CMOS) technologies. In "A New 40-nm FPGA and ASIC Common Platform," Dan Mansur describes Altera's latest advance in FPGA technology. The new devices include features such as improved logic modules, power management through adaptive body biasing, and a combined synthesis flow that lets a design quickly migrate from an FPGA to an application-specific integrated circuit (ASIC) device.
Custom design for mobile voice processing
Application-specific designs lead significant benefits in terms of price, power, and performance that make them attractive for high volume applications. In "Voice Processors Based on the Human Hearing System," Lloyd Watts and his colleagues describe Audience's signal processing chip for noise cancellation in mobile handsets. The system is modeled after the human hearing system and uses a custom set of algorithms and hardware mechanisms to provide noise reduction and echo cancellation in noisy environments.
Space limitations prevent us from including more presentations in this issue. Nevertheless, the presentations from Hot Chips 20 and all previous years are available at http://www.hotchips.org. We encourage you to explore this exciting archive, as well as attend Hot Chips 21 in August of this year.
Christos Kozyrakis is an assistant professor of electrical engineering and computer science at Stanford University. He works on architectures, runtime environments, and programming models for parallel computer systems. His current research focuses on transactional memory, architectural support for security, and power-management techniques. Kozyrakis has a PhD in computer science from the University of California at Berkeley. He is a senior member of the IEEE and the ACM.
Jan-Willem van de Waerdt is chief architect at NXP Semiconductors, where he works on next-generation video processing subsystems for consumer chips. He is the architect of several TriMedia media processors and several types of video processing blocks. He enjoys working in the cross-functional domain of hardware design, compiler/scheduler design, and application-domain-specific optimizations. Van de Waerdt has a PhD in electrical engineering from Delft University of Technology, the Netherlands. He holds 16 patents.
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