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Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
January/February 2009 (vol. 29 no. 1)
pp. 127-138
Xiaoyao Liang, Harvard University
Gu-Yeon Wei, Harvard University
David Brooks, Harvard University

Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a single chip, and microarchitectural blocks within one core. The Revival technique combines the post-fabrication tuning techniques voltage interpolation (VI) and variable latency (VL) to reduce such frequency variations.

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Index Terms:
process variations, voltage interpolation, variable latency
Citation:
Xiaoyao Liang, Gu-Yeon Wei, David Brooks, "Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency," IEEE Micro, vol. 29, no. 1, pp. 127-138, Jan.-Feb. 2009, doi:10.1109/MM.2009.13
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