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| Xiaoyao Liang, Gu-Yeon Wei, David Brooks, "Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency," IEEE Micro, vol. 29, no. 1, pp. 127-138, January/February, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2009.13, author = {Xiaoyao Liang and Gu-Yeon Wei and David Brooks}, title = {Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency}, journal ={IEEE Micro}, volume = {29}, number = {1}, issn = {0272-1732}, year = {2009}, pages = {127-138}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2009.13}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency IS - 1 SN - 0272-1732 SP127 EP138 EPD - 127-138 A1 - Xiaoyao Liang, A1 - Gu-Yeon Wei, A1 - David Brooks, PY - 2009 KW - process variations KW - voltage interpolation KW - variable latency VL - 29 JA - IEEE Micro ER - | |||
Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a single chip, and microarchitectural blocks within one core. The Revival technique combines the post-fabrication tuning techniques voltage interpolation (VI) and variable latency (VL) to reduce such frequency variations.
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