The Community for Technology Leaders
RSS Icon
Issue No.01 - January/February (2009 vol.29)
pp: 127-138
Xiaoyao Liang , Harvard University
Gu-Yeon Wei , Harvard University
David Brooks , Harvard University
<p>Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a single chip, and microarchitectural blocks within one core. The Revival technique combines the post-fabrication tuning techniques voltage interpolation (VI) and variable latency (VL) to reduce such frequency variations.</p>
process variations, voltage interpolation, variable latency
Xiaoyao Liang, Gu-Yeon Wei, David Brooks, "Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency", IEEE Micro, vol.29, no. 1, pp. 127-138, January/February 2009, doi:10.1109/MM.2009.13
11. K. Bowman, S. Duvall, and J. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," J. Solid-State Circuits, vol. 37, no. 2, Feb. 2002, pp. 183-190.
12. X. Liang and D. Brooks, "Mitigating the Impact of Process Variations on Processor Register Files and Execution Units," Proc. 39th IEEE Int'l Symp. Microarchitecture (Micro 06), IEEE CS Press, 2006, pp. 504-514.
13. S. Ozdemir et al., "Yield-Aware Cache Architectures," Proc. 39th IEEE/ACM Int'l Symp. Microarchitecture (Micro 06), IEEE CS Press, 2006, pp. 15-25.
14. A. Tiwari, S.R. Sarangi, and J. Torrellas, "Recycle: Pipeline Adaptation to Tolerate Process Variation," Proc. Int'l Symp. Computer Architecture (ISCA 07), ACM Press, 2007, pp. 323-334.
15. R. Teodorescu et al., "Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing," Proc. 40th IEEE Int'l Symp. Microarchitecture (Micro 07), IEEE CS Press, 2007, pp. 27-42.
16. X. Liang, D. Brooks, and G.-Y. Wei, "A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2008, pp. 404-405.
17. E. Borch et al., "Loose Loops Sink Chips," Proc. 8th Int'l Symp. High-Performance Computer Architecture (HPCA 02), IEEE CS Press, 2002, pp. 299-310.
18. A.J. Bhavnagarwala, X. Tang, and J.D. Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, Apr. 2001, pp. 658-665.
19. A. Agarwal et al., "A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies," IEEE Trans. Very Large Scale Integration Systems, vol. 13, no. 1, Jan. 2005, pp. 27-38.
25 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool