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Issue No.01 - January/February (2009 vol.29)
pp: 96-103
Shih-Lien Lu , Intel
ABSTRACT
<p>Two proposed techniques let microprocessors operate at low voltages despite high memory-cell failure rates. They identify and disable defective portions of the cache at two granularities: individual words or pairs of bits. Both techniques use the entire cache during high-voltage operation while sacrificing cache capacity during low-voltage operation to reduce the minimum voltage below 500 mV.</p>
INDEX TERMS
cache, low-voltage
CITATION
Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu, "Trading Off Cache Capacity for Low-Voltage Operation", IEEE Micro, vol.29, no. 1, pp. 96-103, January/February 2009, doi:10.1109/MM.2009.20
REFERENCES
1. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge Univ. Press, 1998, pp. 144.
2. C. Wilkerson et al., "Trading off Cache Capacity for Reliability to Enable Low Voltage Operation," Proc. 35th Int'l Symp. Computer Architecture (ISCA 35), IEEE CS Press, 2008, pp. 203-214.
3. J.P. Kulkarni, K. Kim, and K. Roy, "A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, Oct. 2007, pp. 2303-2313.
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