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| James Tuck, Wonsun Ahn, Josep Torrellas, Luis Ceze, "SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization," IEEE Micro, vol. 29, no. 1, pp. 84-95, January/February, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/MM.2009.15, author = {James Tuck and Wonsun Ahn and Josep Torrellas and Luis Ceze}, title = {SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization}, journal ={IEEE Micro}, volume = {29}, number = {1}, issn = {0272-1732}, year = {2009}, pages = {84-95}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2009.15}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Micro TI - SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization IS - 1 SN - 0272-1732 SP84 EP95 EPD - 84-95 A1 - James Tuck, A1 - Wonsun Ahn, A1 - Josep Torrellas, A1 - Luis Ceze, PY - 2009 KW - memory disambiguation KW - multicore architectures KW - runtime optimization VL - 29 JA - IEEE Micro ER - | |||
Many code analysis techniques for optimization, debugging, and parallelization must perform runtime disambiguation of address sets. Hardware signatures support such operations efficiently and with low complexity. SoftSig exposes hardware signatures to software through instructions that control which addresses to collect and which to disambiguate against. The Memoise algorithm demonstrates SoftSig's versatility by detecting and eliminating redundant function calls. DOI of original article is available at http://doi.acm.org/10.1145/1346281.1346300
1. D.M. Gallagher et al., "Dynamic Memory Disambiguation Using the Memory Conflict Buffer," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, 1994, pp. 183-193.
2. V. Krishnan and J. Torrellas, "A Chip-Multiprocessor Architecture with Speculative Multithreading," IEEE Trans. Computers, vol. 48, no. 9, Sept. 1999, pp. 866-880.
3. G. Sohi, S. Breach, and T. Vijaykumar, "Multiscalar Processors," Proc. Int'l Symp. Computer Architecture, ACM Press, 1995, pp. 414-425.
4. L. Ceze et al., "Bulk Disambiguation of Speculative Threads in Multiprocessors," Proc. Int'l Symp. Computer Architecture, IEEE CS Press, 2006, pp. 227-238.
5. S. Sethumadhavan et al., "Scalable Hardware Memory Disambiguation for High ILP Processors," Proc. Int'l Symp. Microarchitecture, IEEE CS Press, 2003, p. 399.
6. C. Minh et al., "An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees," Proc. Int'l Symp. Computer Architecture, ACM Press, 2007, pp. 69-80.
7. L. Yen et al., "LogTM-SE: Decoupling Hardware Transactional Memory from Caches," Proc. Int'l Symp. High Performance Computer Architecture, IEEE CS Press, 2007, pp. 261-272.
8. J. Tuck et al., "SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization," Proc Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), ACM Press, 2008, pp. 145-156.
9. Intel Corp., Intel 64 and IA-32 Architectures Software Developer's Manual. Vol. 3B: System Programming Guide, Part II, 2007.
10. Y. Ding and Z. Li, "A Compiler Scheme for Reusing Intermediate Computation Results," Proc. Int'l Symp. Code Generation and Optimization, IEEE CS Press, 2004, p. 279.
11. C.-K. Luk et al., "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation," Proc. Int'l Conf. Programming Language Design and Implementation, ACM Press, 2005, pp. 190-200.
12. J. Renau et al., "SESC Simulator," 2005; http:/sesc.sourceforge.net.