Issue No.01 - January/February (2009 vol.29)
Onur Mutlu , Carnegie Mellon University
Thomas Moscibroda , Microsoft Research
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2009.12
<p>Uncontrolled interthread interference in main memory can destroy individual threads' memory-level parallelism, effectively serializing the memory requests of a thread whose latencies would otherwise have largely overlapped, thereby reducing single-thread performance. The parallelism-aware batch scheduler preserves each thread's memory-level parallelism, ensures fairness and starvation freedom, and supports system-level thread priorities.</p>
memory controllers, DRAM, memory-level parallelism, fairness, multicore, quality of service, chip multiprocessors.
Onur Mutlu, Thomas Moscibroda, "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers", IEEE Micro, vol.29, no. 1, pp. 22-32, January/February 2009, doi:10.1109/MM.2009.12